3 files changed, 70 insertions, 0 deletions
diff --git a/testsuite/gna/issue2136/repro1.vhdl b/testsuite/gna/issue2136/repro1.vhdl
new file mode 100644
index 000000000..7c7867b53
--- /dev/null
+++ b/testsuite/gna/issue2136/repro1.vhdl
@@ -0,0 +1,24 @@
+entity repro1 is
+end;
+
+architecture BHV of repro1 is
+  type matrixType is array(natural range <>) of bit_vector;
+
+  function get_min( a : matrixType) return bit_vector is
+    variable res    : a'element;
+  begin
+    res:=a(a'left);
+    return res;
+  end function get_min;
+
+  signal matrix1 : matrixType(0 to 1)(7 downto 0):=(x"80",x"10");
+begin
+
+  process
+    variable min1    : bit_vector  (7 downto 0);
+  begin
+    min1 := get_min(matrix1);
+    assert min1 = x"80" severity failure;
+    wait;
+  end process;
+end;
diff --git a/testsuite/gna/issue2136/test.vhdl b/testsuite/gna/issue2136/test.vhdl
new file mode 100644
index 000000000..12560eaaa
--- /dev/null
+++ b/testsuite/gna/issue2136/test.vhdl
@@ -0,0 +1,32 @@
+library ieee;
+use ieee.std_logic_1164.all;
+--use ieee.std_logic_arith.all;
+--use ieee.std_logic_unsigned.all;
+
+entity test is
+end;
+
+architecture BHV of test is
+  type matrixType is array(natural range <>) of std_logic_vector;
+
+  function get_min( a : matrixType) return std_logic_vector is
+    variable res    : a'element;
+  begin
+    report "a: " & natural'image(a'left) & natural'image (a'right);
+    res:=a(a'left);
+    for i in a'range loop
+      if (a(i)<res) then
+        res:=a(i);
+      end if;
+    end loop;
+    return res;
+  end function get_min;
+
+  signal matrix1 : matrixType(0 to 1)(7 downto 0):=(x"80",x"10");
+  signal min1    : std_logic_vector  (7 downto 0);
+
+begin
+
+  min1 <= get_min(matrix1);
+
+end;
diff --git a/testsuite/gna/issue2136/testsuite.sh b/testsuite/gna/issue2136/testsuite.sh
new file mode 100755
index 000000000..29e47c32c
--- /dev/null
+++ b/testsuite/gna/issue2136/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze repro1.vhdl
+elab_simulate repro1
+
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"