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-rw-r--r--src/synth/synth-context.adb11
-rw-r--r--src/synth/synth-decls.adb6
-rw-r--r--src/synth/synth-expr.adb2
-rw-r--r--src/synth/synth-stmts.adb45
-rw-r--r--src/synth/synth-stmts.ads2
-rw-r--r--src/synth/synth-values.adb4
-rw-r--r--src/synth/synth-values.ads4
7 files changed, 40 insertions, 34 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 8cbecd305..2a219a904 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -563,9 +563,14 @@ package body Synth.Context is
declare
Res : Net;
begin
- Res := Get_Current_Value (Build_Context, Val.A_Wid);
- return Build_Extract (Build_Context, Res, Val.A_Off,
- Get_Type_Width (Val.Typ));
+ if Val.A_Obj.Kind = Value_Wire then
+ Res := Get_Current_Value (Build_Context, Val.A_Obj.W);
+ return Build_Extract (Build_Context, Res, Val.A_Off,
+ Get_Type_Width (Val.Typ));
+ else
+ pragma Assert (Val.A_Off = 0);
+ return Get_Net (Val.A_Obj);
+ end if;
end;
when others =>
raise Internal_Error;
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 57953ce9f..ba6d2d238 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -524,14 +524,14 @@ package body Synth.Decls is
when Iir_Kind_Object_Alias_Declaration =>
Synth_Declaration_Type (Syn_Inst, Decl);
declare
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
Typ : Type_Acc;
begin
Stmts.Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl),
- Wid, Off, Typ);
+ Obj, Off, Typ);
Create_Object (Syn_Inst, Decl,
- Create_Value_Alias (Wid, Off, Typ));
+ Create_Value_Alias (Obj, Off, Typ));
end;
when Iir_Kind_Anonymous_Signal_Declaration =>
Make_Object (Syn_Inst, Wire_Signal, Decl);
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 7129eb90f..82ceedfa2 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -709,7 +709,7 @@ package body Synth.Expr is
when Value_Net =>
return Create_Value_Net (Val.N, Ntype);
when Value_Alias =>
- return Create_Value_Alias (Val.A_Wid, Val.A_Off, Ntype);
+ return Create_Value_Alias (Val.A_Obj, Val.A_Off, Ntype);
when others =>
raise Internal_Error;
end case;
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index f1cb13d2c..57a155a9f 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -118,14 +118,14 @@ package body Synth.Stmts is
procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc;
Pfx : Node;
- Dest_Wid : out Wire_Id;
+ Dest_Obj : out Value_Acc;
Dest_Off : out Uns32;
Dest_Type : out Type_Acc) is
begin
case Get_Kind (Pfx) is
when Iir_Kind_Simple_Name =>
Synth_Assignment_Prefix (Syn_Inst, Get_Named_Entity (Pfx),
- Dest_Wid, Dest_Off, Dest_Type);
+ Dest_Obj, Dest_Off, Dest_Type);
when Iir_Kind_Interface_Signal_Declaration
| Iir_Kind_Variable_Declaration
| Iir_Kind_Signal_Declaration
@@ -133,7 +133,7 @@ package body Synth.Stmts is
declare
Targ : constant Value_Acc := Get_Value (Syn_Inst, Pfx);
begin
- Dest_Wid := Targ.W;
+ Dest_Obj := Targ;
Dest_Off := 0;
Dest_Type := Targ.Typ;
end;
@@ -141,7 +141,7 @@ package body Synth.Stmts is
declare
Targ : constant Value_Acc := Get_Value (Syn_Inst, Pfx);
begin
- Dest_Wid := Targ.A_Wid;
+ Dest_Obj := Targ.A_Obj;
Dest_Off := Targ.A_Off;
Dest_Type := Targ.Typ;
end;
@@ -153,7 +153,7 @@ package body Synth.Stmts is
W : Width;
begin
Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Pfx),
- Dest_Wid, Dest_Off, Dest_Type);
+ Dest_Obj, Dest_Off, Dest_Type);
Synth_Indexed_Name
(Syn_Inst, Pfx, Dest_Type, Voff, Mul, Off, W);
@@ -176,7 +176,7 @@ package body Synth.Stmts is
Get_Element_Position (Get_Named_Entity (Pfx));
begin
Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Pfx),
- Dest_Wid, Dest_Off, Dest_Type);
+ Dest_Obj, Dest_Off, Dest_Type);
Dest_Off := Dest_Off + Dest_Type.Rec.E (Idx + 1).Off;
Dest_Type := Dest_Type.Rec.E (Idx + 1).Typ;
end;
@@ -190,7 +190,7 @@ package body Synth.Stmts is
Wd : Uns32;
begin
Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Pfx),
- Dest_Wid, Dest_Off, Dest_Type);
+ Dest_Obj, Dest_Off, Dest_Type);
Synth_Slice_Suffix (Syn_Inst, Pfx, Dest_Type.Vbound,
Res_Bnd, Inp, Step, Sl_Off, Wd);
@@ -219,7 +219,7 @@ package body Synth.Stmts is
case Kind is
when Target_Simple =>
-- For a simple target, the destination is known.
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
when Target_Aggregate =>
-- For an aggregate: the type is computed and the details will
@@ -263,19 +263,19 @@ package body Synth.Stmts is
| Iir_Kind_Signal_Declaration
| Iir_Kind_Anonymous_Signal_Declaration =>
declare
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
Typ : Type_Acc;
begin
- Synth_Assignment_Prefix (Syn_Inst, Target, Wid, Off, Typ);
+ Synth_Assignment_Prefix (Syn_Inst, Target, Obj, Off, Typ);
return Target_Info'(Kind => Target_Simple,
Targ_Type => Typ,
- Wid => Wid,
+ Obj => Obj,
Off => Off);
end;
when Iir_Kind_Indexed_Name =>
declare
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
Typ : Type_Acc;
El_Typ : Type_Acc;
@@ -289,7 +289,7 @@ package body Synth.Stmts is
V : Net;
begin
Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Target),
- Wid, Off, Typ);
+ Obj, Off, Typ);
Synth_Indexed_Name (Syn_Inst, Target, Typ,
Voff, Mul, Idx_Off, W);
El_Typ := Get_Array_Element (Typ);
@@ -299,25 +299,25 @@ package body Synth.Stmts is
pragma Assert (Mul = 0);
return Target_Info'(Kind => Target_Simple,
Targ_Type => El_Typ,
- Wid => Wid,
+ Obj => Obj,
Off => Off + Idx_Off);
else
Targ_Net := Get_Current_Assign_Value
- (Build_Context, Wid, Off, Get_Type_Width (Typ));
+ (Build_Context, Obj.W, Off, Get_Type_Width (Typ));
V := Build_Dyn_Insert
(Build_Context, Targ_Net, No_Net,
Voff, Mul, Int32 (Idx_Off));
Set_Location (V, Target);
return Target_Info'(Kind => Target_Memory,
Targ_Type => El_Typ,
- Mem_Wid => Wid,
+ Mem_Wid => Obj.W,
Mem_Off => Off,
Mem_Val => V);
end if;
end;
when Iir_Kind_Slice_Name =>
declare
- Wid : Wire_Id;
+ Obj : Value_Acc;
Off : Uns32;
Typ : Type_Acc;
@@ -332,26 +332,26 @@ package body Synth.Stmts is
V : Net;
begin
Synth_Assignment_Prefix (Syn_Inst, Get_Prefix (Target),
- Wid, Off, Typ);
+ Obj, Off, Typ);
Synth_Slice_Suffix (Syn_Inst, Target, Typ.Vbound,
Res_Bnd, Inp, Step, Sl_Off, Wd);
Res_Type := Create_Vector_Type (Res_Bnd, Typ.Vec_El);
if Inp /= No_Net then
Targ_Net := Get_Current_Assign_Value
- (Build_Context, Wid, Off, Get_Type_Width (Typ));
+ (Build_Context, Obj.W, Off, Get_Type_Width (Typ));
V := Build_Dyn_Insert
(Build_Context, Targ_Net, No_Net,
Inp, Step, Sl_Off);
Set_Location (V, Target);
return Target_Info'(Kind => Target_Memory,
Targ_Type => Res_Type,
- Mem_Wid => Wid,
+ Mem_Wid => Obj.W,
Mem_Off => Off,
Mem_Val => V);
else
return Target_Info'(Kind => Target_Simple,
Targ_Type => Res_Type,
- Wid => Wid,
+ Obj => Obj,
Off => Off + Uns32 (Sl_Off));
end if;
end;
@@ -370,7 +370,8 @@ package body Synth.Stmts is
Synth_Assignment_Aggregate
(Syn_Inst, Target.Aggr, Target.Targ_Type, Val, Loc);
when Target_Simple =>
- Synth_Assign (Target.Wid, Target.Targ_Type, Val, Target.Off, Loc);
+ Synth_Assign (Target.Obj.W, Target.Targ_Type,
+ Val, Target.Off, Loc);
when Target_Memory =>
declare
Inst : constant Instance := Get_Net_Parent (Target.Mem_Val);
diff --git a/src/synth/synth-stmts.ads b/src/synth/synth-stmts.ads
index 0e4c2860d..c583328c0 100644
--- a/src/synth/synth-stmts.ads
+++ b/src/synth/synth-stmts.ads
@@ -35,7 +35,7 @@ package Synth.Stmts is
procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc;
Pfx : Node;
- Dest_Wid : out Wire_Id;
+ Dest_Obj : out Value_Acc;
Dest_Off : out Uns32;
Dest_Type : out Type_Acc);
diff --git a/src/synth/synth-values.adb b/src/synth/synth-values.adb
index 166bd9e43..030ceec81 100644
--- a/src/synth/synth-values.adb
+++ b/src/synth/synth-values.adb
@@ -548,7 +548,7 @@ package body Synth.Values is
(Kind => Value_Subtype, Typ => Typ)));
end Create_Value_Subtype;
- function Create_Value_Alias (Wid : Wire_Id; Off : Uns32; Typ : Type_Acc)
+ function Create_Value_Alias (Obj : Value_Acc; Off : Uns32; Typ : Type_Acc)
return Value_Acc
is
subtype Value_Type_Alias is Value_Type (Value_Alias);
@@ -556,7 +556,7 @@ package body Synth.Values is
begin
return To_Value_Acc (Alloc (Current_Pool,
(Kind => Value_Alias,
- A_Wid => Wid,
+ A_Obj => Obj,
A_Off => Off,
Typ => Typ)));
end Create_Value_Alias;
diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads
index c79e989b3..09a5df1d4 100644
--- a/src/synth/synth-values.ads
+++ b/src/synth/synth-values.ads
@@ -204,7 +204,7 @@ package Synth.Values is
when Value_Instance =>
Instance : Instance_Id;
when Value_Alias =>
- A_Wid : Wire_Id;
+ A_Obj : Value_Acc;
A_Off : Uns32;
end case;
end record;
@@ -283,7 +283,7 @@ package Synth.Values is
function Create_Value_Instance (Inst : Instance_Id) return Value_Acc;
- function Create_Value_Alias (Wid : Wire_Id; Off : Uns32; Typ : Type_Acc)
+ function Create_Value_Alias (Obj : Value_Acc; Off : Uns32; Typ : Type_Acc)
return Value_Acc;
function Unshare (Src : Value_Acc; Pool : Areapool_Acc)
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-03 01:40:47 +0000