3 files changed, 143 insertions, 0 deletions
diff --git a/testsuite/synth/issue1348/sdp_simple.vhdl b/testsuite/synth/issue1348/sdp_simple.vhdl
new file mode 100644
index 000000000..58513dd4a
--- /dev/null
+++ b/testsuite/synth/issue1348/sdp_simple.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all,
+    ieee.numeric_std.all;
+
+entity sdp_simple is
+    port (
+        clk          : in  std_logic;
+
+        read_a       : in  std_logic;
+        write_a      : in  std_logic;
+        byteen_a     : in  std_logic_vector(0 downto 0);
+        addr_a       : in  std_logic_vector(11 downto 0);
+        data_read_a  : out std_logic_vector(7 downto 0);
+        data_write_a : in  std_logic_vector(7 downto 0);
+
+        read_b       : in  std_logic;
+        write_b      : in  std_logic;
+        byteen_b     : in  std_logic_vector(3 downto 0);
+        addr_b       : in  std_logic_vector(9 downto 0);
+        data_read_b  : out std_logic_vector(31 downto 0);
+        data_write_b : in  std_logic_vector(31 downto 0)
+    );
+end sdp_simple;
+
+architecture behavioral of sdp_simple is
+    type ram_t is array(0 to 4095) of std_logic_vector(7 downto 0);
+    signal store : ram_t := (others => (others => '0'));
+begin
+    process(clk)
+    begin
+        if rising_edge(clk) then
+            if write_a = '1' and byteen_a(0) = '1' then
+                store(to_integer(unsigned(addr_a))) <= data_write_a;
+            end if;
+
+            if read_a = '1' then
+                data_read_a <= store(to_integer(unsigned(addr_a)));
+            end if;
+
+            for i in 0 to 3 loop
+                if write_b = '1' and byteen_b(i) = '1' then
+                    store(to_integer(unsigned(addr_b) & to_unsigned(i, 2))) <=
+                        data_write_b((i+1) * 8 - 1 downto i * 8);
+                end if;
+
+                if read_b = '1' then
+                    data_read_b((i+1) * 8 - 1 downto i * 8) <=
+                        store(to_integer(unsigned(addr_b) & to_unsigned(i, 2)));
+                end if;
+            end loop;
+        end if;
+    end process;
+end behavioral;
diff --git a/testsuite/synth/issue1348/tb_sdp_simple.vhdl b/testsuite/synth/issue1348/tb_sdp_simple.vhdl
new file mode 100644
index 000000000..0b5de91de
--- /dev/null
+++ b/testsuite/synth/issue1348/tb_sdp_simple.vhdl
@@ -0,0 +1,83 @@
+entity tb_sdp_simple is
+end tb_sdp_simple;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_sdp_simple is
+  signal clk          : std_logic;
+  
+  signal read_a       : std_logic;
+  signal write_a      : std_logic;
+  signal byteen_a     : std_logic_vector(0 downto 0);
+  signal addr_a       : std_logic_vector(11 downto 0);
+  signal data_read_a  : std_logic_vector(7 downto 0);
+  signal data_write_a : std_logic_vector(7 downto 0);
+
+  signal read_b       : std_logic;
+  signal write_b      : std_logic;
+  signal byteen_b     : std_logic_vector(3 downto 0);
+  signal addr_b       : std_logic_vector(9 downto 0);
+  signal data_read_b  : std_logic_vector(31 downto 0);
+  signal data_write_b : std_logic_vector(31 downto 0);
+begin
+  sdp_simple_2: entity work.sdp_simple
+    port map (
+      clk          => clk,
+      read_a       => read_a,
+      write_a      => write_a,
+      byteen_a     => byteen_a,
+      addr_a       => addr_a,
+      data_read_a  => data_read_a,
+      data_write_a => data_write_a,
+      read_b       => read_b,
+      write_b      => write_b,
+      byteen_b     => byteen_b,
+      addr_b       => addr_b,
+      data_read_b  => data_read_b,
+      data_write_b => data_write_b);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    clk <= '0';
+    write_a <= '0';
+
+    write_b <= '1';
+    read_b <= '0';
+    addr_b <= b"00_0000_0000";
+    byteen_b <= "1111";
+    data_write_b <= x"d3_c2_b1_a0";
+    pulse;
+
+    write_b <= '0';
+    write_a <= '0';
+    read_a <= '1';
+    addr_a <= x"001";
+    pulse;
+    assert data_read_a = x"b1" severity failure;
+
+    write_b <= '0';
+    write_a <= '1';
+    read_a <= '0';
+    byteen_a <= "1";
+    addr_a <= x"000";
+    data_write_a <= x"10";
+    pulse;
+
+    write_a <= '0';
+    write_b <= '0';
+    read_b <= '1';
+    addr_b <= b"00_0000_0000";
+    pulse;
+    assert data_read_b = x"d3_c2_b1_10" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1348/testsuite.sh b/testsuite/synth/issue1348/testsuite.sh
new file mode 100755
index 000000000..713fab53f
--- /dev/null
+++ b/testsuite/synth/issue1348/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_tb sdp_simple
+
+echo "Test successful"