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-rw-r--r--src/vhdl/translate/trans-chap3.adb40
-rw-r--r--src/vhdl/vhdl-sem_expr.adb5
2 files changed, 31 insertions, 14 deletions
diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb
index 12916d12b..ce01f0a26 100644
--- a/src/vhdl/translate/trans-chap3.adb
+++ b/src/vhdl/translate/trans-chap3.adb
@@ -1175,13 +1175,18 @@ package body Trans.Chap3 is
procedure Translate_Array_Subtype_Definition (Def : Iir)
is
Parent_Type : constant Iir := Get_Parent_Type (Def);
- Parent_El_Type : constant Iir := Get_Element_Subtype (Parent_Type);
El_Type : constant Iir := Get_Element_Subtype (Def);
El_Tinfo : Type_Info_Acc;
Mark : Id_Mark_Type;
begin
-- Handle element subtype.
- if Get_Array_Element_Constraint (Def) /= Null_Iir then
+ El_Tinfo := Get_Info (El_Type);
+ if El_Tinfo = null then
+ -- Usually, if the array element subtype was not yet translated,
+ -- it's because it is defined by the array subtype (the array
+ -- subtype adds constraints to the elements).
+ -- However, for an aggregate, the array type may not be the owner.
+
-- Do not create vars for element subtype, but use
-- the layout field of the array vars.
Push_Identifier_Prefix (Mark, "ET");
@@ -1189,16 +1194,27 @@ package body Trans.Chap3 is
Pop_Identifier_Prefix (Mark);
El_Tinfo := Get_Info (El_Type);
- if Is_Composite (El_Tinfo) then
- pragma Assert (El_Tinfo.S.Composite_Layout = Null_Var);
- El_Tinfo.S.Subtype_Owner := Get_Info (Def);
- end if;
- elsif Get_Info (El_Type) = null then
- -- if the element subtype is created for this subtype, be sure it
- -- has infos.
- -- FIXME: the test should be refined. There can be a new element
- -- subtype because a resolver has been added.
- Set_Info (El_Type, Get_Info (Parent_El_Type));
+ case El_Tinfo.S.Kind is
+ when Kind_Type_Array
+ | Kind_Type_Record =>
+ pragma Assert (El_Tinfo.S.Composite_Layout = Null_Var);
+ El_Tinfo.S.Subtype_Owner := Get_Info (Def);
+ when Kind_Type_Scalar =>
+ if El_Tinfo.S.Range_Var = Null_Var then
+ -- Happen only for subtypes of enumeration type ?
+ declare
+ El_Parent_Type : constant Iir :=
+ Get_Element_Subtype (Parent_Type);
+ El_Parent_Tinfo : constant Type_Info_Acc :=
+ Get_Info (El_Parent_Type);
+ begin
+ El_Tinfo.S.Range_Var := El_Parent_Tinfo.S.Range_Var;
+ end;
+ end if;
+ when Kind_Type_File
+ | Kind_Type_Protected =>
+ raise Internal_Error;
+ end case;
end if;
if Get_Constraint_State (Def) = Fully_Constrained then
diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb
index 0f46a8687..091bf0a0b 100644
--- a/src/vhdl/vhdl-sem_expr.adb
+++ b/src/vhdl/vhdl-sem_expr.adb
@@ -3579,7 +3579,8 @@ package body Vhdl.Sem_Expr is
-- TODO: try to extract the 'best' element subtype: with
-- static indexes, with constrained sub-elements.
-- Possibly create an hybrid subtype (for records).
- if Get_Index_Constraint_Flag (New_El_Subtype) then
+ if Get_Constraint_State (New_El_Subtype) = Fully_Constrained
+ then
El_Subtype := New_El_Subtype;
return;
end if;
@@ -4090,7 +4091,7 @@ package body Vhdl.Sem_Expr is
else
A_Subtype := Create_Array_Subtype (Base_Type, Get_Location (Aggr));
Set_Element_Subtype (A_Subtype, El_Subtype);
- if El_Subtype /= El_Type then
+ if False and then El_Subtype /= El_Type then
-- If the element subtype is defined by an element of the
-- aggregate, move the ownership to the aggregate type.
Sem_Array_Aggregate_Move_Element_Subtype_Owner
n262' href='#n262'>262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586
```
yosys -- Yosys Open SYnthesis Suite

Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>

Permission to use, copy, modify, and/or distribute this software for any
purpose with or without fee is hereby granted, provided that the above
copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
```


yosys – Yosys Open SYnthesis Suite
===================================

This is a framework for RTL synthesis tools. It currently has
extensive Verilog-2005 support and provides a basic set of
synthesis algorithms for various application domains.

Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
adding additional passes as needed by extending the yosys C++
code base.

Yosys is free software licensed under the ISC license (a GPL
compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).


Web Site and Other Resources
============================

More information and documentation can be found on the Yosys web site:
- http://www.clifford.at/yosys/

The "Documentation" page on the web site contains links to more resources,
including a manual that even describes some of the Yosys internals:
- http://www.clifford.at/yosys/documentation.html

The file `CodingReadme` in this directory contains additional information
for people interested in using the Yosys C++ APIs.

Users interested in formal verification might want to use the formal verification
front-end for Yosys, SymbiYosys:
- https://symbiyosys.readthedocs.io/en/latest/
- https://github.com/YosysHQ/SymbiYosys


Setup
======

You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make.
TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile).
Xdot (graphviz) is used by the ``show`` command in yosys to display schematics.

For example on Ubuntu Linux 16.04 LTS the following commands will install all
prerequisites for building yosys:

	$ sudo apt-get install build-essential clang bison flex \
		libreadline-dev gawk tcl-dev libffi-dev git \