diff options
| -rw-r--r-- | src/synth/synth-ieee-numeric_std.adb | 13 | ||||
| -rw-r--r-- | src/synth/synth-ieee-numeric_std.ads | 2 | ||||
| -rw-r--r-- | src/synth/synth-static_oper.adb | 16 | ||||
| -rw-r--r-- | testsuite/synth/issue1179/bug.vhdl | 7 |
4 files changed, 36 insertions, 2 deletions
diff --git a/src/synth/synth-ieee-numeric_std.adb b/src/synth/synth-ieee-numeric_std.adb index d997c93b8..96a228bb3 100644 --- a/src/synth/synth-ieee-numeric_std.adb +++ b/src/synth/synth-ieee-numeric_std.adb @@ -279,6 +279,19 @@ package body Synth.Ieee.Numeric_Std is return Mul_Uns_Uns (T, R); end Mul_Nat_Uns; + function Mul_Uns_Nat (L : Std_Logic_Vector; R : Uns64) + return Std_Logic_Vector + is + pragma Assert (L'First = 1); + T : Std_Logic_Vector (1 .. L'Last); + begin + if L'Last < 1 then + return Null_Vec; + end if; + To_Unsigned (T, R); + return Mul_Uns_Uns (L, T); + end Mul_Uns_Nat; + function Mul_Sgn_Sgn (L, R : Std_Logic_Vector) return Std_Logic_Vector is pragma Assert (L'First = 1); diff --git a/src/synth/synth-ieee-numeric_std.ads b/src/synth/synth-ieee-numeric_std.ads index f0004c846..7e85f04a0 100644 --- a/src/synth/synth-ieee-numeric_std.ads +++ b/src/synth/synth-ieee-numeric_std.ads @@ -42,6 +42,8 @@ package Synth.Ieee.Numeric_Std is function Mul_Uns_Uns (L, R : Std_Logic_Vector) return Std_Logic_Vector; function Mul_Nat_Uns (L : Uns64; R : Std_Logic_Vector) return Std_Logic_Vector; + function Mul_Uns_Nat (L : Std_Logic_Vector; R : Uns64) + return Std_Logic_Vector; function Mul_Sgn_Sgn (L, R : Std_Logic_Vector) return Std_Logic_Vector; end Synth.Ieee.Numeric_Std; diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 4d4ff8305..4712dd844 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -462,6 +462,20 @@ package body Synth.Static_Oper is end; end Synth_Mul_Nat_Uns; + function Synth_Mul_Uns_Nat (L, R : Valtyp; Loc : Syn_Src) return Valtyp + is + pragma Unreferenced (Loc); + L_Arr : Std_Logic_Vector (1 .. Natural (Vec_Length (L.Typ))); + R_Val : constant Uns64 := Uns64 (Read_Discrete (R)); + begin + To_Std_Logic_Vector (L, L_Arr); + declare + Res_Arr : constant Std_Logic_Vector := Mul_Uns_Nat (L_Arr, R_Val); + begin + return To_Valtyp (Res_Arr, L.Typ.Vec_El); + end; + end Synth_Mul_Uns_Nat; + function Synth_Mul_Sgn_Sgn (L, R : Valtyp; Loc : Syn_Src) return Valtyp is pragma Unreferenced (Loc); @@ -904,6 +918,8 @@ package body Synth.Static_Oper is return Synth_Mul_Uns_Uns (Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Nat_Uns => return Synth_Mul_Nat_Uns (Left, Right, Expr); + when Iir_Predefined_Ieee_Numeric_Std_Mul_Uns_Nat => + return Synth_Mul_Uns_Nat (Left, Right, Expr); when Iir_Predefined_Ieee_Numeric_Std_Mul_Sgn_Sgn => return Synth_Mul_Sgn_Sgn (Left, Right, Expr); diff --git a/testsuite/synth/issue1179/bug.vhdl b/testsuite/synth/issue1179/bug.vhdl index a4271b91f..70f7a8eca 100644 --- a/testsuite/synth/issue1179/bug.vhdl +++ b/testsuite/synth/issue1179/bug.vhdl @@ -4,7 +4,8 @@ use IEEE.numeric_std.all; entity bug is port( - dummy : out positive + m0 : out positive; + m1 : out positive ); end bug; @@ -12,7 +13,9 @@ architecture behav of bug is constant A : positive := 4; constant B : positive := 1100; constant C : positive := to_integer(A * to_unsigned(B, 11)); + constant D : positive := to_integer(to_unsigned(B, 11) * A); begin - dummy <= c; + m0 <= c; + m1 <= d; end architecture; |