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-rw-r--r--src/grt/grt-fst.adb12
-rw-r--r--src/grt/grt-vcd.adb62
-rw-r--r--src/grt/grt-vcd.ads10
-rw-r--r--src/grt/grt-vpi.adb18
4 files changed, 48 insertions, 54 deletions
diff --git a/src/grt/grt-fst.adb b/src/grt/grt-fst.adb
index bd7b9a940..e6d9e6721 100644
--- a/src/grt/grt-fst.adb
+++ b/src/grt/grt-fst.adb
@@ -128,15 +128,10 @@ package body Grt.Fst is
begin
Get_Verilog_Wire (Sig, Vcd_El);
- if Vcd_El.Kind = Vcd_Bad then
- -- Not handled.
- return;
- end if;
-
-
case Vcd_El.Kind is
when Vcd_Bad =>
- raise Program_Error;
+ -- Not handled.
+ return;
when Vcd_Bool =>
Vt := FST_VT_VCD_REG;
Len := 1;
@@ -333,12 +328,11 @@ package body Grt.Fst is
From_Bit : constant array (Ghdl_B1) of Character := "01";
type Map_Type is array (Ghdl_E8 range 0 .. 8) of Character;
From_Std : constant Map_Type := "UX01ZWLH-";
- Sig : Signal_Arr_Ptr;
V : Fst_Sig_Info renames Fst_Table.Table (I);
Len : Ghdl_Index_Type;
Hand : constant fstHandle := V.Hand;
+ Sig : constant Signal_Arr_Ptr := V.Wire.Sigs;
begin
- Sig := To_Signal_Arr_Ptr (V.Wire.Addr);
if V.Wire.Irange = null then
Len := 1;
else
diff --git a/src/grt/grt-vcd.adb b/src/grt/grt-vcd.adb
index 13c1f20d5..de8b99f8c 100644
--- a/src/grt/grt-vcd.adb
+++ b/src/grt/grt-vcd.adb
@@ -22,6 +22,8 @@
-- covered by the GNU General Public License. This exception does not
-- however invalidate any other reasons why the executable file might be
-- covered by the GNU Public License.
+
+with System; use System;
with Interfaces;
with Grt.Stdio; use Grt.Stdio;
with System.Storage_Elements; -- Work around GNAT bug.
@@ -319,7 +321,7 @@ package body Grt.Vcd is
| Ghdl_Rtik_Type_E8
| Ghdl_Rtik_Subtype_Scalar =>
Info.Kind := Rti_To_Vcd_Kind (Rti);
- Info.Addr := Sig_Addr;
+ Info.Sigs := To_Signal_Arr_Ptr (Sig_Addr);
Info.Irange := null;
when Ghdl_Rtik_Subtype_Array =>
declare
@@ -327,7 +329,7 @@ package body Grt.Vcd is
begin
St := To_Ghdl_Rtin_Subtype_Array_Acc (Rti);
Info.Kind := Rti_To_Vcd_Kind (St.Basetype);
- Info.Addr := Sig_Addr;
+ Info.Sigs := To_Signal_Arr_Ptr (Sig_Addr);
Info.Irange := To_Ghdl_Range_Ptr
(Loc_To_Addr (St.Common.Depth, St.Bounds,
Avhpi_Get_Context (Sig)));
@@ -339,7 +341,7 @@ package body Grt.Vcd is
Info.Kind := Rti_To_Vcd_Kind
(To_Ghdl_Rtin_Type_Array_Acc (Rti));
Uc := To_Ghdl_Uc_Array_Acc (Sig_Addr);
- Info.Addr := Uc.Base;
+ Info.Sigs := To_Signal_Arr_Ptr (Uc.Base);
Info.Irange := To_Ghdl_Range_Ptr (Uc.Bounds);
end;
when others =>
@@ -370,6 +372,16 @@ package body Grt.Vcd is
end if;
end Get_Verilog_Wire;
+ function Get_Wire_Length (Info : Verilog_Wire_Info)
+ return Ghdl_Index_Type is
+ begin
+ if Info.Irange = null then
+ return 1;
+ else
+ return Info.Irange.I32.Len;
+ end if;
+ end Get_Wire_Length;
+
procedure Add_Signal (Sig : VhpiHandleT)
is
N : Vcd_Index_Type;
@@ -632,42 +644,35 @@ package body Grt.Vcd is
procedure Vcd_Put_Var (I : Vcd_Index_Type)
is
- Addr : Address;
V : Verilog_Wire_Info renames Vcd_Table.Table (I);
- Len : Ghdl_Index_Type;
+ Len : constant Ghdl_Index_Type := Get_Wire_Length (V);
begin
- Addr := V.Addr;
- if V.Irange = null then
- Len := 1;
- else
- Len := V.Irange.I32.Len;
- end if;
case V.Val is
when Vcd_Effective =>
case V.Kind is
when Vcd_Bit
| Vcd_Bool =>
- Vcd_Put_Bit (To_Signal_Arr_Ptr (Addr)(0).Value.B1);
+ Vcd_Put_Bit (V.Sigs (0).Value.B1);
when Vcd_Stdlogic =>
- Vcd_Put_Stdlogic (To_Signal_Arr_Ptr (Addr)(0).Value.E8);
+ Vcd_Put_Stdlogic (V.Sigs (0).Value.E8);
when Vcd_Integer32 =>
Vcd_Putc ('b');
- Vcd_Put_Integer32 (To_Signal_Arr_Ptr (Addr)(0).Value.E32);
+ Vcd_Put_Integer32 (V.Sigs (0).Value.E32);
Vcd_Putc (' ');
when Vcd_Float64 =>
Vcd_Putc ('r');
- Vcd_Put_Float64 (To_Signal_Arr_Ptr (Addr)(0).Value.F64);
+ Vcd_Put_Float64 (V.Sigs (0).Value.F64);
Vcd_Putc (' ');
when Vcd_Bitvector =>
Vcd_Putc ('b');
for J in 0 .. Len - 1 loop
- Vcd_Put_Bit (To_Signal_Arr_Ptr (Addr)(J).Value.B1);
+ Vcd_Put_Bit (V.Sigs (J).Value.B1);
end loop;
Vcd_Putc (' ');
when Vcd_Stdlogic_Vector =>
Vcd_Putc ('b');
for J in 0 .. Len - 1 loop
- Vcd_Put_Stdlogic (To_Signal_Arr_Ptr (Addr)(J).Value.E8);
+ Vcd_Put_Stdlogic (V.Sigs (J).Value.E8);
end loop;
Vcd_Putc (' ');
when Vcd_Bad =>
@@ -677,33 +682,27 @@ package body Grt.Vcd is
case V.Kind is
when Vcd_Bit
| Vcd_Bool =>
- Vcd_Put_Bit
- (To_Signal_Arr_Ptr (Addr)(0).Driving_Value.B1);
+ Vcd_Put_Bit (V.Sigs (0).Driving_Value.B1);
when Vcd_Stdlogic =>
- Vcd_Put_Stdlogic
- (To_Signal_Arr_Ptr (Addr)(0).Driving_Value.E8);
+ Vcd_Put_Stdlogic (V.Sigs (0).Driving_Value.E8);
when Vcd_Integer32 =>
Vcd_Putc ('b');
- Vcd_Put_Integer32
- (To_Signal_Arr_Ptr (Addr)(0).Driving_Value.E32);
+ Vcd_Put_Integer32 (V.Sigs (0).Driving_Value.E32);
Vcd_Putc (' ');
when Vcd_Float64 =>
Vcd_Putc ('r');
- Vcd_Put_Float64 (To_Signal_Arr_Ptr (Addr)(0)
- .Driving_Value.F64);
+ Vcd_Put_Float64 (V.Sigs (0).Driving_Value.F64);
Vcd_Putc (' ');
when Vcd_Bitvector =>
Vcd_Putc ('b');
for J in 0 .. Len - 1 loop
- Vcd_Put_Bit
- (To_Signal_Arr_Ptr (Addr)(J).Driving_Value.B1);
+ Vcd_Put_Bit (V.Sigs (J).Driving_Value.B1);
end loop;
Vcd_Putc (' ');
when Vcd_Stdlogic_Vector =>
Vcd_Putc ('b');
for J in 0 .. Len - 1 loop
- Vcd_Put_Stdlogic
- (To_Signal_Arr_Ptr (Addr)(J).Driving_Value.E8);
+ Vcd_Put_Stdlogic (V.Sigs (J).Driving_Value.E8);
end loop;
Vcd_Putc (' ');
when Vcd_Bad =>
@@ -736,7 +735,7 @@ package body Grt.Vcd is
| Vcd_Integer32
| Vcd_Float64 =>
for J in 0 .. Len - 1 loop
- if To_Signal_Arr_Ptr (Info.Addr)(J).Last_Event = Last then
+ if Info.Sigs (J).Last_Event = Last then
return True;
end if;
end loop;
@@ -753,8 +752,7 @@ package body Grt.Vcd is
| Vcd_Integer32
| Vcd_Float64 =>
for J in 0 .. Len - 1 loop
- if To_Signal_Arr_Ptr (Info.Addr)(J).Last_Active = Last
- then
+ if Info.Sigs (J).Last_Active = Last then
return True;
end if;
end loop;
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads
index 73096c5dd..a3561f534 100644
--- a/src/grt/grt-vcd.ads
+++ b/src/grt/grt-vcd.ads
@@ -22,9 +22,10 @@
-- covered by the GNU General Public License. This exception does not
-- however invalidate any other reasons why the executable file might be
-- covered by the GNU Public License.
-with System; use System;
+
with Grt.Types; use Grt.Types;
with Grt.Avhpi; use Grt.Avhpi;
+with Grt.Signals;
package Grt.Vcd is
-- Abstract type for IO.
@@ -47,8 +48,8 @@ package Grt.Vcd is
type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving);
type Verilog_Wire_Info is record
- -- Signal address
- Addr : Address;
+ -- Access to an array of signals.
+ Sigs : Grt.Signals.Signal_Arr_Ptr;
Irange : Ghdl_Range_Ptr;
Kind : Vcd_Var_Kind;
@@ -58,6 +59,9 @@ package Grt.Vcd is
procedure Get_Verilog_Wire (Sig : VhpiHandleT;
Info : out Verilog_Wire_Info);
+ -- Number of signals in INFO (at least one).
+ function Get_Wire_Length (Info : Verilog_Wire_Info) return Ghdl_Index_Type;
+
-- Return TRUE if last change time of the wire described by INFO is LAST.
function Verilog_Wire_Changed (Info : Verilog_Wire_Info;
Last : Std_Time)
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb
index 9b77319f1..37cc714f6 100644
--- a/src/grt/grt-vpi.adb
+++ b/src/grt/grt-vpi.adb
@@ -424,14 +424,12 @@ package body Grt.Vpi is
| Vcd_Bool
| Vcd_Bitvector =>
for J in 0 .. Len - 1 loop
- ii_vpi_get_value_bin_str_B1
- (To_Signal_Arr_Ptr (Info.Addr)(J).Value.B1);
+ ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value.B1);
end loop;
when Vcd_Stdlogic
| Vcd_Stdlogic_Vector =>
for J in 0 .. Len - 1 loop
- ii_vpi_get_value_bin_str_E8
- (To_Signal_Arr_Ptr (Info.Addr)(J).Value.E8);
+ ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value.E8);
end loop;
end case;
when Vcd_Driving =>
@@ -445,13 +443,13 @@ package body Grt.Vpi is
| Vcd_Bitvector =>
for J in 0 .. Len - 1 loop
ii_vpi_get_value_bin_str_B1
- (To_Signal_Arr_Ptr (Info.Addr)(J).Driving_Value.B1);
+ (Info.Sigs (J).Driving_Value.B1);
end loop;
when Vcd_Stdlogic
| Vcd_Stdlogic_Vector =>
for J in 0 .. Len - 1 loop
ii_vpi_get_value_bin_str_E8
- (To_Signal_Arr_Ptr (Info.Addr)(J).Driving_Value.E8);
+ (Info.Sigs (J).Driving_Value.E8);
end loop;
end case;
end case;
@@ -626,14 +624,14 @@ package body Grt.Vpi is
| Vcd_Bool
| Vcd_Bitvector =>
for J in 0 .. Len - 1 loop
- ii_vpi_put_value_bin_str_B1(
- To_Signal_Arr_Ptr(Info.Addr)(J), ValueStr(Integer(J+1)));
+ ii_vpi_put_value_bin_str_B1
+ (Info.Sigs (J), ValueStr (Integer (J + 1)));
end loop;
when Vcd_Stdlogic
| Vcd_Stdlogic_Vector =>
for J in 0 .. Len - 1 loop
- ii_vpi_put_value_bin_str_E8(
- To_Signal_Arr_Ptr(Info.Addr)(J), ValueStr(Integer(J+1)));
+ ii_vpi_put_value_bin_str_E8
+ (Info.Sigs (J), ValueStr (Integer (J + 1)));
end loop;
when Vcd_Integer32
| Vcd_Float64 =>
generated by cgit v1.2.3 (git 2.25.1) at 2024-08-27 07:16:39 +0000