5 files changed, 111 insertions, 0 deletions
diff --git a/testsuite/synth/func01/func01.vhdl b/testsuite/synth/func01/func01.vhdl
new file mode 100644
index 000000000..67d203907
--- /dev/null
+++ b/testsuite/synth/func01/func01.vhdl
@@ -0,0 +1,30 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func01 is
+  generic (l : natural := 3);
+  port (a : std_logic_vector (7 downto 0);
+        sel : std_logic;
+        b : out std_logic_vector (7 downto 0));
+end func01;
+
+architecture behav of func01 is
+  function gen_mask (len : natural) return std_logic_vector is
+    variable res : std_logic_vector (7 downto 0);
+  begin
+    res := (others => '0');
+    res (len downto 0) := (others => '1');
+    return res;
+  end gen_mask;
+
+begin
+  process (a, sel)
+  begin
+    if sel = '1' then
+      b <= a and gen_mask (l);
+    else
+      b <= a;
+    end if;
+  end process;
+end behav;
+    
diff --git a/testsuite/synth/func01/func02.vhdl b/testsuite/synth/func01/func02.vhdl
new file mode 100644
index 000000000..9476c9130
--- /dev/null
+++ b/testsuite/synth/func01/func02.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func02 is
+  port (a : std_logic_vector (7 downto 0);
+        b : out std_logic_vector (7 downto 0));
+end func02;
+
+architecture behav of func02 is
+  function gen_mask (len : natural) return std_logic_vector is
+    variable res : std_logic_vector (len - 1 downto 0);
+  begin
+    res := (0 => '1', others => '0');
+    return res;
+  end gen_mask;
+
+begin
+  b <= a and gen_mask (8);
+end behav;
+    
diff --git a/testsuite/synth/func01/func03.vhdl b/testsuite/synth/func01/func03.vhdl
new file mode 100644
index 000000000..10022c9cb
--- /dev/null
+++ b/testsuite/synth/func01/func03.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity func03 is
+  port (a : std_logic_vector (7 downto 0);
+        b : out std_logic_vector (7 downto 0));
+end func03;
+
+architecture behav of func03 is
+  function gen_mask (len : natural) return std_logic_vector is
+    variable res : std_logic_vector (len - 1 downto 0);
+  begin
+    res := (0 => '1', others => '0');
+    return res;
+  end gen_mask;
+  constant mask : std_logic_vector(7 downto 0) := gen_mask (8);
+begin
+  b <= a and mask;
+end behav;
+    
diff --git a/testsuite/synth/func01/tb_func03.vhdl b/testsuite/synth/func01/tb_func03.vhdl
new file mode 100644
index 000000000..d9ef0c0eb
--- /dev/null
+++ b/testsuite/synth/func01/tb_func03.vhdl
@@ -0,0 +1,25 @@
+entity tb_func03 is
+end tb_func03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func03 is
+  signal a, b : std_logic_vector(7 downto 0);
+begin
+  dut: entity work.func03
+    port map (a, b);
+
+  process
+  begin
+    a <= x"ff";
+    wait for 1 ns;
+    assert b = x"01" severity failure;
+
+    a <= x"ee";
+    wait for 1 ns;
+    assert b = x"00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/testsuite.sh b/testsuite/synth/func01/testsuite.sh
new file mode 100755
index 000000000..e947b0e10
--- /dev/null
+++ b/testsuite/synth/func01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in func03; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"