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-rw-r--r--src/simul/simul-vhdl_elab.adb2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb
index b2b0a4f2d..4948152cc 100644
--- a/src/simul/simul-vhdl_elab.adb
+++ b/src/simul/simul-vhdl_elab.adb
@@ -615,6 +615,7 @@ package body Simul.Vhdl_Elab is
return;
end if;
when Iir_Kind_Psl_Assert_Directive
+ | Iir_Kind_Psl_Assume_Directive
| Iir_Kind_Psl_Cover_Directive =>
List := Get_PSL_Clock_Sensitivity (Proc);
Gather_Sensitivity (Inst, Proc_Idx, List);
@@ -904,6 +905,7 @@ package body Simul.Vhdl_Elab is
| Iir_Kind_Psl_Declaration =>
null;
when Iir_Kind_Psl_Assert_Directive
+ | Iir_Kind_Psl_Assume_Directive
| Iir_Kind_Psl_Cover_Directive
| Iir_Kind_Concurrent_Break_Statement =>
Processes_Table.Append ((Proc => Stmt,