diff options
| -rw-r--r-- | python/libghdl/thin/vhdl/nodes.py | 261 | ||||
| -rw-r--r-- | src/synth/synth-oper.adb | 11 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 165 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 2 |
4 files changed, 225 insertions, 214 deletions
diff --git a/python/libghdl/thin/vhdl/nodes.py b/python/libghdl/thin/vhdl/nodes.py index 08f2ab3ed..9b6d03977 100644 --- a/python/libghdl/thin/vhdl/nodes.py +++ b/python/libghdl/thin/vhdl/nodes.py @@ -1446,136 +1446,137 @@ class Iir_Predefined: Ieee_Std_Logic_Signed_Sub_Slv_Log = 453 Ieee_Std_Logic_Signed_Sub_Log_Slv = 454 Ieee_Std_Logic_Signed_Mul_Slv_Slv = 455 - Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 456 - Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 457 - Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 458 - Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 459 - Ieee_Std_Logic_Arith_Conv_Integer_Int = 460 - Ieee_Std_Logic_Arith_Conv_Integer_Uns = 461 - Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 462 - Ieee_Std_Logic_Arith_Conv_Integer_Log = 463 - Ieee_Std_Logic_Arith_Conv_Vector_Int = 464 - Ieee_Std_Logic_Arith_Conv_Vector_Uns = 465 - Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 466 - Ieee_Std_Logic_Arith_Conv_Vector_Log = 467 - Ieee_Std_Logic_Arith_Ext = 468 - Ieee_Std_Logic_Arith_Sxt = 469 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 470 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 471 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 472 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 473 - Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 474 - Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 475 - Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 476 - Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 477 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 478 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 479 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 480 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 481 - Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 482 - Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 483 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 484 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 485 - Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 486 - Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 487 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 488 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 489 - Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 490 - Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 491 - Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 492 - Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 493 - Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 494 - Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 495 - Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 496 - Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 497 - Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 498 - Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 499 - Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 500 - Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 501 - Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns = 502 - Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn = 503 - Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn = 504 - Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn = 505 - Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns = 506 - Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns = 507 - Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn = 508 - Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn = 509 - Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns = 510 - Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns = 511 - Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn = 512 - Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn = 513 - Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv = 514 - Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv = 515 - Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv = 516 - Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv = 517 - Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv = 518 - Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv = 519 - Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv = 520 - Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv = 521 - Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv = 522 - Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv = 523 - Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv = 524 - Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv = 525 - Ieee_Std_Logic_Arith_Lt_Uns_Uns = 526 - Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 527 - Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 528 - Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 529 - Ieee_Std_Logic_Arith_Lt_Uns_Int = 530 - Ieee_Std_Logic_Arith_Lt_Int_Uns = 531 - Ieee_Std_Logic_Arith_Lt_Sgn_Int = 532 - Ieee_Std_Logic_Arith_Lt_Int_Sgn = 533 - Ieee_Std_Logic_Arith_Le_Uns_Uns = 534 - Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 535 - Ieee_Std_Logic_Arith_Le_Uns_Sgn = 536 - Ieee_Std_Logic_Arith_Le_Sgn_Uns = 537 - Ieee_Std_Logic_Arith_Le_Uns_Int = 538 - Ieee_Std_Logic_Arith_Le_Int_Uns = 539 - Ieee_Std_Logic_Arith_Le_Sgn_Int = 540 - Ieee_Std_Logic_Arith_Le_Int_Sgn = 541 - Ieee_Std_Logic_Arith_Gt_Uns_Uns = 542 - Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 543 - Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 544 - Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 545 - Ieee_Std_Logic_Arith_Gt_Uns_Int = 546 - Ieee_Std_Logic_Arith_Gt_Int_Uns = 547 - Ieee_Std_Logic_Arith_Gt_Sgn_Int = 548 - Ieee_Std_Logic_Arith_Gt_Int_Sgn = 549 - Ieee_Std_Logic_Arith_Ge_Uns_Uns = 550 - Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 551 - Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 552 - Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 553 - Ieee_Std_Logic_Arith_Ge_Uns_Int = 554 - Ieee_Std_Logic_Arith_Ge_Int_Uns = 555 - Ieee_Std_Logic_Arith_Ge_Sgn_Int = 556 - Ieee_Std_Logic_Arith_Ge_Int_Sgn = 557 - Ieee_Std_Logic_Arith_Eq_Uns_Uns = 558 - Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 559 - Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 560 - Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 561 - Ieee_Std_Logic_Arith_Eq_Uns_Int = 562 - Ieee_Std_Logic_Arith_Eq_Int_Uns = 563 - Ieee_Std_Logic_Arith_Eq_Sgn_Int = 564 - Ieee_Std_Logic_Arith_Eq_Int_Sgn = 565 - Ieee_Std_Logic_Arith_Ne_Uns_Uns = 566 - Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 567 - Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 568 - Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 569 - Ieee_Std_Logic_Arith_Ne_Uns_Int = 570 - Ieee_Std_Logic_Arith_Ne_Int_Uns = 571 - Ieee_Std_Logic_Arith_Ne_Sgn_Int = 572 - Ieee_Std_Logic_Arith_Ne_Int_Sgn = 573 - Ieee_Std_Logic_Misc_And_Reduce_Slv = 574 - Ieee_Std_Logic_Misc_And_Reduce_Suv = 575 - Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 576 - Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 577 - Ieee_Std_Logic_Misc_Or_Reduce_Slv = 578 - Ieee_Std_Logic_Misc_Or_Reduce_Suv = 579 - Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 580 - Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 581 - Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 582 - Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 583 - Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 584 - Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 585 + Ieee_Std_Logic_Signed_Conv_Integer = 456 + Ieee_Std_Logic_Arith_Conv_Unsigned_Int = 457 + Ieee_Std_Logic_Arith_Conv_Unsigned_Uns = 458 + Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn = 459 + Ieee_Std_Logic_Arith_Conv_Unsigned_Log = 460 + Ieee_Std_Logic_Arith_Conv_Integer_Int = 461 + Ieee_Std_Logic_Arith_Conv_Integer_Uns = 462 + Ieee_Std_Logic_Arith_Conv_Integer_Sgn = 463 + Ieee_Std_Logic_Arith_Conv_Integer_Log = 464 + Ieee_Std_Logic_Arith_Conv_Vector_Int = 465 + Ieee_Std_Logic_Arith_Conv_Vector_Uns = 466 + Ieee_Std_Logic_Arith_Conv_Vector_Sgn = 467 + Ieee_Std_Logic_Arith_Conv_Vector_Log = 468 + Ieee_Std_Logic_Arith_Ext = 469 + Ieee_Std_Logic_Arith_Sxt = 470 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns = 471 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn = 472 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn = 473 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Sgn = 474 + Ieee_Std_Logic_Arith_Mul_Uns_Uns_Slv = 475 + Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Slv = 476 + Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Slv = 477 + Ieee_Std_Logic_Arith_Mul_Uns_Sgn_Slv = 478 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Uns = 479 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Sgn = 480 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Sgn = 481 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Sgn = 482 + Ieee_Std_Logic_Arith_Add_Uns_Int_Uns = 483 + Ieee_Std_Logic_Arith_Add_Int_Uns_Uns = 484 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Sgn = 485 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Sgn = 486 + Ieee_Std_Logic_Arith_Add_Uns_Log_Uns = 487 + Ieee_Std_Logic_Arith_Add_Log_Uns_Uns = 488 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Sgn = 489 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Sgn = 490 + Ieee_Std_Logic_Arith_Add_Uns_Uns_Slv = 491 + Ieee_Std_Logic_Arith_Add_Sgn_Sgn_Slv = 492 + Ieee_Std_Logic_Arith_Add_Uns_Sgn_Slv = 493 + Ieee_Std_Logic_Arith_Add_Sgn_Uns_Slv = 494 + Ieee_Std_Logic_Arith_Add_Uns_Int_Slv = 495 + Ieee_Std_Logic_Arith_Add_Int_Uns_Slv = 496 + Ieee_Std_Logic_Arith_Add_Sgn_Int_Slv = 497 + Ieee_Std_Logic_Arith_Add_Int_Sgn_Slv = 498 + Ieee_Std_Logic_Arith_Add_Uns_Log_Slv = 499 + Ieee_Std_Logic_Arith_Add_Log_Uns_Slv = 500 + Ieee_Std_Logic_Arith_Add_Sgn_Log_Slv = 501 + Ieee_Std_Logic_Arith_Add_Log_Sgn_Slv = 502 + Ieee_Std_Logic_Arith_Sub_Uns_Uns_Uns = 503 + Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Sgn = 504 + Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Sgn = 505 + Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Sgn = 506 + Ieee_Std_Logic_Arith_Sub_Uns_Int_Uns = 507 + Ieee_Std_Logic_Arith_Sub_Int_Uns_Uns = 508 + Ieee_Std_Logic_Arith_Sub_Sgn_Int_Sgn = 509 + Ieee_Std_Logic_Arith_Sub_Int_Sgn_Sgn = 510 + Ieee_Std_Logic_Arith_Sub_Uns_Log_Uns = 511 + Ieee_Std_Logic_Arith_Sub_Log_Uns_Uns = 512 + Ieee_Std_Logic_Arith_Sub_Sgn_Log_Sgn = 513 + Ieee_Std_Logic_Arith_Sub_Log_Sgn_Sgn = 514 + Ieee_Std_Logic_Arith_Sub_Uns_Uns_Slv = 515 + Ieee_Std_Logic_Arith_Sub_Sgn_Sgn_Slv = 516 + Ieee_Std_Logic_Arith_Sub_Uns_Sgn_Slv = 517 + Ieee_Std_Logic_Arith_Sub_Sgn_Uns_Slv = 518 + Ieee_Std_Logic_Arith_Sub_Uns_Int_Slv = 519 + Ieee_Std_Logic_Arith_Sub_Int_Uns_Slv = 520 + Ieee_Std_Logic_Arith_Sub_Sgn_Int_Slv = 521 + Ieee_Std_Logic_Arith_Sub_Int_Sgn_Slv = 522 + Ieee_Std_Logic_Arith_Sub_Uns_Log_Slv = 523 + Ieee_Std_Logic_Arith_Sub_Log_Uns_Slv = 524 + Ieee_Std_Logic_Arith_Sub_Sgn_Log_Slv = 525 + Ieee_Std_Logic_Arith_Sub_Log_Sgn_Slv = 526 + Ieee_Std_Logic_Arith_Lt_Uns_Uns = 527 + Ieee_Std_Logic_Arith_Lt_Sgn_Sgn = 528 + Ieee_Std_Logic_Arith_Lt_Uns_Sgn = 529 + Ieee_Std_Logic_Arith_Lt_Sgn_Uns = 530 + Ieee_Std_Logic_Arith_Lt_Uns_Int = 531 + Ieee_Std_Logic_Arith_Lt_Int_Uns = 532 + Ieee_Std_Logic_Arith_Lt_Sgn_Int = 533 + Ieee_Std_Logic_Arith_Lt_Int_Sgn = 534 + Ieee_Std_Logic_Arith_Le_Uns_Uns = 535 + Ieee_Std_Logic_Arith_Le_Sgn_Sgn = 536 + Ieee_Std_Logic_Arith_Le_Uns_Sgn = 537 + Ieee_Std_Logic_Arith_Le_Sgn_Uns = 538 + Ieee_Std_Logic_Arith_Le_Uns_Int = 539 + Ieee_Std_Logic_Arith_Le_Int_Uns = 540 + Ieee_Std_Logic_Arith_Le_Sgn_Int = 541 + Ieee_Std_Logic_Arith_Le_Int_Sgn = 542 + Ieee_Std_Logic_Arith_Gt_Uns_Uns = 543 + Ieee_Std_Logic_Arith_Gt_Sgn_Sgn = 544 + Ieee_Std_Logic_Arith_Gt_Uns_Sgn = 545 + Ieee_Std_Logic_Arith_Gt_Sgn_Uns = 546 + Ieee_Std_Logic_Arith_Gt_Uns_Int = 547 + Ieee_Std_Logic_Arith_Gt_Int_Uns = 548 + Ieee_Std_Logic_Arith_Gt_Sgn_Int = 549 + Ieee_Std_Logic_Arith_Gt_Int_Sgn = 550 + Ieee_Std_Logic_Arith_Ge_Uns_Uns = 551 + Ieee_Std_Logic_Arith_Ge_Sgn_Sgn = 552 + Ieee_Std_Logic_Arith_Ge_Uns_Sgn = 553 + Ieee_Std_Logic_Arith_Ge_Sgn_Uns = 554 + Ieee_Std_Logic_Arith_Ge_Uns_Int = 555 + Ieee_Std_Logic_Arith_Ge_Int_Uns = 556 + Ieee_Std_Logic_Arith_Ge_Sgn_Int = 557 + Ieee_Std_Logic_Arith_Ge_Int_Sgn = 558 + Ieee_Std_Logic_Arith_Eq_Uns_Uns = 559 + Ieee_Std_Logic_Arith_Eq_Sgn_Sgn = 560 + Ieee_Std_Logic_Arith_Eq_Uns_Sgn = 561 + Ieee_Std_Logic_Arith_Eq_Sgn_Uns = 562 + Ieee_Std_Logic_Arith_Eq_Uns_Int = 563 + Ieee_Std_Logic_Arith_Eq_Int_Uns = 564 + Ieee_Std_Logic_Arith_Eq_Sgn_Int = 565 + Ieee_Std_Logic_Arith_Eq_Int_Sgn = 566 + Ieee_Std_Logic_Arith_Ne_Uns_Uns = 567 + Ieee_Std_Logic_Arith_Ne_Sgn_Sgn = 568 + Ieee_Std_Logic_Arith_Ne_Uns_Sgn = 569 + Ieee_Std_Logic_Arith_Ne_Sgn_Uns = 570 + Ieee_Std_Logic_Arith_Ne_Uns_Int = 571 + Ieee_Std_Logic_Arith_Ne_Int_Uns = 572 + Ieee_Std_Logic_Arith_Ne_Sgn_Int = 573 + Ieee_Std_Logic_Arith_Ne_Int_Sgn = 574 + Ieee_Std_Logic_Misc_And_Reduce_Slv = 575 + Ieee_Std_Logic_Misc_And_Reduce_Suv = 576 + Ieee_Std_Logic_Misc_Nand_Reduce_Slv = 577 + Ieee_Std_Logic_Misc_Nand_Reduce_Suv = 578 + Ieee_Std_Logic_Misc_Or_Reduce_Slv = 579 + Ieee_Std_Logic_Misc_Or_Reduce_Suv = 580 + Ieee_Std_Logic_Misc_Nor_Reduce_Slv = 581 + Ieee_Std_Logic_Misc_Nor_Reduce_Suv = 582 + Ieee_Std_Logic_Misc_Xor_Reduce_Slv = 583 + Ieee_Std_Logic_Misc_Xor_Reduce_Suv = 584 + Ieee_Std_Logic_Misc_Xnor_Reduce_Slv = 585 + Ieee_Std_Logic_Misc_Xnor_Reduce_Suv = 586 Get_Kind = libghdl.vhdl__nodes__get_kind Get_Location = libghdl.vhdl__nodes__get_location diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index 42c17af9b..e63baebe8 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1615,21 +1615,22 @@ package body Synth.Oper is return Create_Value_Net (Get_Net (Ctxt, L), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int => return Synth_Conv_Vector (False); when Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => return Synth_Conv_Vector (True); when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log - | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Log + | Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer => -- UNSIGNED to Natural. return Create_Value_Net (Synth_Uresize (Ctxt, Get_Net (Ctxt, L), Res_Typ.W, Expr), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Toint_Sgn_Int - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn + | Iir_Predefined_Ieee_Std_Logic_Signed_Conv_Integer => -- SIGNED to Integer. return Create_Value_Net (Synth_Sresize (Ctxt, L, Res_Typ.W, Expr), Res_Typ); diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 0fcc45911..3eb76cd11 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -1,4 +1,4 @@ --- Nodes recognizer for ieee.numeric_std and ieee.numeric_bit. +-- Nodes recognizer for ieee.std_logic_unsigned and ieee.std_logic_signed -- Copyright (C) 2016 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under @@ -96,26 +96,23 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Error : exception; - procedure Extract_Declarations - (Pkg : Iir_Package_Declaration; Sign : Sign_Kind) + procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind) + is + Arg_Type : constant Iir := Get_Type (Arg); + begin + if Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then + Kind := Arg_Int; + elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type then + Kind := Arg_Log; + elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then + Kind := Arg_Slv; + else + raise Error; + end if; + end Classify_Arg; + + procedure Extract_Declaration (Decl : Iir; Sign : Sign_Kind) is - procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind) - is - Arg_Type : constant Iir := Get_Type (Arg); - begin - if Arg_Type = Vhdl.Std_Package.Integer_Subtype_Definition then - Kind := Arg_Int; - elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Type then - Kind := Arg_Log; - elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then - Kind := Arg_Slv; - else - raise Error; - end if; - end Classify_Arg; - - Decl : Iir; - Arg1, Arg2 : Iir; Arg1_Kind, Arg2_Kind : Arg_Kind; @@ -156,6 +153,74 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Res : Iir_Predefined_Functions; begin + Arg1 := Get_Interface_Declaration_Chain (Decl); + if Is_Null (Arg1) then + raise Error; + end if; + + Res := Iir_Predefined_None; + + Classify_Arg (Arg1, Arg1_Kind); + Arg2 := Get_Chain (Arg1); + if Is_Valid (Arg2) then + -- Dyadic function. + Classify_Arg (Arg2, Arg2_Kind); + + case Get_Identifier (Decl) is + when Name_Op_Equality => + Res := Handle_Binary (Eq_Patterns, None_Patterns); + when Name_Op_Inequality => + Res := Handle_Binary (Ne_Patterns, None_Patterns); + when Name_Op_Less => + Res := Handle_Binary (Lt_Patterns, None_Patterns); + when Name_Op_Less_Equal => + Res := Handle_Binary (Le_Patterns, None_Patterns); + when Name_Op_Greater => + Res := Handle_Binary (Gt_Patterns, None_Patterns); + when Name_Op_Greater_Equal => + Res := Handle_Binary (Ge_Patterns, None_Patterns); + when Name_Op_Plus => + Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); + when Name_Op_Minus => + Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns); + when Name_Op_Mul => + case Sign is + when Pkg_Unsigned => + pragma Assert (Arg1_Kind = Arg_Slv); + pragma Assert (Arg2_Kind = Arg_Slv); + Res := Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv; + when Pkg_Signed => + pragma Assert (Arg1_Kind = Arg_Slv); + pragma Assert (Arg2_Kind = Arg_Slv); + Res := + Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv; + end case; + when others => + null; + end case; + else + -- Monadic function. + case Get_Identifier (Decl) is + when Name_Conv_Integer => + case Sign is + when Pkg_Unsigned => + Res := + Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer; + when Pkg_Signed => + Res := Iir_Predefined_Ieee_Std_Logic_Signed_Conv_Integer; + end case; + when others => + null; + end case; + end if; + Set_Implicit_Definition (Decl, Res); + end Extract_Declaration; + + procedure Extract_Declarations + (Pkg : Iir_Package_Declaration; Sign : Sign_Kind) + is + Decl : Iir; + begin Decl := Get_Declaration_Chain (Pkg); -- Handle functions. @@ -164,67 +229,9 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is raise Error; end if; - Arg1 := Get_Interface_Declaration_Chain (Decl); - if Is_Null (Arg1) then - raise Error; - end if; + Extract_Declaration (Decl, Sign); - Res := Iir_Predefined_None; - - Classify_Arg (Arg1, Arg1_Kind); - Arg2 := Get_Chain (Arg1); - if Is_Valid (Arg2) then - -- Dyadic function. - Classify_Arg (Arg2, Arg2_Kind); - - case Get_Identifier (Decl) is - when Name_Op_Equality => - Res := Handle_Binary (Eq_Patterns, None_Patterns); - when Name_Op_Inequality => - Res := Handle_Binary (Ne_Patterns, None_Patterns); - when Name_Op_Less => - Res := Handle_Binary (Lt_Patterns, None_Patterns); - when Name_Op_Less_Equal => - Res := Handle_Binary (Le_Patterns, None_Patterns); - when Name_Op_Greater => - Res := Handle_Binary (Gt_Patterns, None_Patterns); - when Name_Op_Greater_Equal => - Res := Handle_Binary (Ge_Patterns, None_Patterns); - when Name_Op_Plus => - Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); - when Name_Op_Minus => - Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns); - when Name_Op_Mul => - case Sign is - when Pkg_Unsigned => - pragma Assert (Arg1_Kind = Arg_Slv); - pragma Assert (Arg2_Kind = Arg_Slv); - Res := - Iir_Predefined_Ieee_Std_Logic_Unsigned_Mul_Slv_Slv; - when Pkg_Signed => - pragma Assert (Arg1_Kind = Arg_Slv); - pragma Assert (Arg2_Kind = Arg_Slv); - Res := - Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv; - end case; - when others => - null; - end case; - else - -- Monadic function. - case Get_Identifier (Decl) is - when Name_Conv_Integer => - if Sign = Pkg_Unsigned then - Res := - Iir_Predefined_Ieee_Std_Logic_Unsigned_Conv_Integer; - end if; - when others => - null; - end case; - end if; - Set_Implicit_Definition (Decl, Res); Decl := Get_Chain (Decl); end loop; end Extract_Declarations; - end Vhdl.Ieee.Std_Logic_Unsigned; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 07faf5b7b..889f8ad70 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5831,6 +5831,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Signed_Mul_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Conv_Integer, + -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, |