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-rw-r--r--testsuite/gna/issue616/mwe.vhdl76
-rw-r--r--testsuite/gna/issue616/repro.vhdl16
-rw-r--r--testsuite/gna/issue616/repro1.vhdl16
-rw-r--r--testsuite/gna/issue616/repro2.vhdl18
-rwxr-xr-xtestsuite/gna/issue616/testsuite.sh14
5 files changed, 140 insertions, 0 deletions
diff --git a/testsuite/gna/issue616/mwe.vhdl b/testsuite/gna/issue616/mwe.vhdl
new file mode 100644
index 000000000..c791e1218
--- /dev/null
+++ b/testsuite/gna/issue616/mwe.vhdl
@@ -0,0 +1,76 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity mwe is
+ generic (
+ wait_us : integer := 400;
+ clk_period : time := 10 ns
+ );
+end entity;
+
+architecture sim of mwe is
+
+ signal clk : std_logic := '0';
+ signal runsim : boolean := true;
+
+ function slv_all(constant width : in integer; constant value : in std_logic) return std_logic_vector is
+ variable slv_v : std_logic_vector(width - 1 downto 0) := (others => value);
+ begin
+ return slv_v;
+ end function;
+
+ function slv_ones(constant width : in integer) return std_logic_vector is
+ begin
+ return slv_all(width, '1');
+ end function;
+
+
+begin
+
+ p_clk: process
+ begin
+ while runsim loop
+ clk <= '0';
+ wait for clk_period / 2;
+ clk <= '1';
+ wait for clk_period / 2;
+ end loop;
+ wait;
+ end process;
+
+
+ p_check_requests: process
+
+ function return_true return boolean is
+ constant ones_c : std_logic_vector(31 downto 0) := slv_ones(32);
+ begin
+ return true;
+ end function;
+
+ variable ones_v : std_logic_vector(31 downto 0);
+ variable result_v : boolean;
+ begin
+ wait until rising_edge(clk);
+
+ while runsim loop
+ wait until rising_edge(clk);
+
+ result_v := return_true;
+
+ -- uncommenting the following lines speeds up the design
+ -- ones_v := slv_ones(32);
+
+ end loop;
+
+ wait;
+ end process;
+
+
+ p_main: process
+ begin
+ wait for wait_us * 1 us;
+ runsim <= false;
+ wait;
+ end process;
+
+end architecture;
diff --git a/testsuite/gna/issue616/repro.vhdl b/testsuite/gna/issue616/repro.vhdl
new file mode 100644
index 000000000..1632bb056
--- /dev/null
+++ b/testsuite/gna/issue616/repro.vhdl
@@ -0,0 +1,16 @@
+package repro is
+ function return_true return boolean;
+end repro;
+
+package body repro is
+ function slv_ones(constant width : in integer) return bit_vector is
+ begin
+ return (1 to width => '1');
+ end function;
+
+ function return_true return boolean is
+ constant ones_c : bit_vector(31 downto 0) := slv_ones(32);
+ begin
+ return true;
+ end function;
+end repro;
diff --git a/testsuite/gna/issue616/repro1.vhdl b/testsuite/gna/issue616/repro1.vhdl
new file mode 100644
index 000000000..9df4513ff
--- /dev/null
+++ b/testsuite/gna/issue616/repro1.vhdl
@@ -0,0 +1,16 @@
+package repro1 is
+ function return_true return boolean;
+end repro1;
+
+package body repro1 is
+ function slv_ones(constant width : in integer) return bit_vector is
+ begin
+ return (1 to width => '1');
+ end function;
+
+ function return_true return boolean is
+ constant ones_c : bit_vector(31 downto 0) := (others => '1');
+ begin
+ return ones_c = slv_ones(32);
+ end function;
+end repro1;
diff --git a/testsuite/gna/issue616/repro2.vhdl b/testsuite/gna/issue616/repro2.vhdl
new file mode 100644
index 000000000..b7060a2cb
--- /dev/null
+++ b/testsuite/gna/issue616/repro2.vhdl
@@ -0,0 +1,18 @@
+package repro2 is
+ procedure return_true (res : out boolean);
+end repro2;
+
+package body repro2 is
+ function slv_ones(constant width : in integer) return bit_vector is
+ begin
+ return (1 to width => '1');
+ end function;
+
+ procedure return_true (res : out boolean) is
+ constant ones_c : bit_vector(31 downto 0) := (others => '1');
+ constant two_c : bit_vector := slv_ones(32);
+ begin
+ wait for 1 ns;
+ res := ones_c = two_c;
+ end;
+end repro2;
diff --git a/testsuite/gna/issue616/testsuite.sh b/testsuite/gna/issue616/testsuite.sh
new file mode 100755
index 000000000..d84196e87
--- /dev/null
+++ b/testsuite/gna/issue616/testsuite.sh
@@ -0,0 +1,14 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+# Not very interesting, need to observe memory usage.
+analyze mwe.vhdl
+elab_simulate mwe
+
+analyze repro.vhdl
+analyze repro1.vhdl
+
+clean
+
+echo "Test successful"