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-rw-r--r--src/synth/netlists-builders.adb12
-rw-r--r--src/synth/netlists-builders.ads4
-rw-r--r--src/synth/netlists-disp_vhdl.adb2
-rw-r--r--src/synth/netlists-gates.ads2
-rw-r--r--src/synth/synth-expr.adb6
5 files changed, 13 insertions, 13 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 73c86929b..d17547491 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -253,9 +253,9 @@ package body Netlists.Builders is
Res : Module;
begin
Res := New_User_Module
- (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("memidx1")),
- Id_Memidx1, 1, 1, 2);
- Ctxt.M_Memidx1 := Res;
+ (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("memidx")),
+ Id_Memidx, 1, 1, 2);
+ Ctxt.M_Memidx := Res;
Outputs := (0 => Create_Output ("o"));
Inputs (0) := Create_Input ("i");
Set_Port_Desc (Res, Inputs (0 .. 0), Outputs);
@@ -977,7 +977,7 @@ package body Netlists.Builders is
return O;
end Build_Dyn_Insert;
- function Build_Memidx1
+ function Build_Memidx
(Ctxt : Context_Acc;
I : Net; Step : Uns32; Max : Uns32; W : Width) return Net
is
@@ -987,14 +987,14 @@ package body Netlists.Builders is
Inst : Instance;
O : Net;
begin
- Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memidx1);
+ Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memidx);
O := Get_Output (Inst, 0);
Set_Width (O, W);
Connect (Get_Input (Inst, 0), I);
Set_Param_Uns32 (Inst, 0, Step);
Set_Param_Uns32 (Inst, 1, Max);
return O;
- end Build_Memidx1;
+ end Build_Memidx;
function Build_Addidx (Ctxt : Context_Acc; L, R : Net) return Net
is
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index fc8d65dd4..be580d392 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -134,7 +134,7 @@ package Netlists.Builders is
function Build_Dyn_Insert
(Ctxt : Context_Acc; I : Net; V : Net; P : Net; Off : Uns32) return Net;
- function Build_Memidx1
+ function Build_Memidx
(Ctxt : Context_Acc;
I : Net; Step : Uns32; Max : Uns32; W : Width) return Net;
function Build_Addidx (Ctxt : Context_Acc; L, R : Net) return Net;
@@ -207,7 +207,7 @@ private
M_Extract : Module;
M_Dyn_Extract : Module;
M_Dyn_Insert : Module;
- M_Memidx1 : Module;
+ M_Memidx : Module;
M_Addidx : Module;
M_Assert : Module;
M_Assume : Module;
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index 1aa362b08..883f181cf 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -586,7 +586,7 @@ package body Netlists.Disp_Vhdl is
Disp_Template (" \o0 <= ", Inst);
Disp_Extract (Inst);
Put_Line (";");
- when Id_Memidx1 =>
+ when Id_Memidx =>
declare
O : constant Net := Get_Output (Inst, 0);
Wd : constant Width := Get_Width (O);
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 067c6d7c7..7e4339e22 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -154,7 +154,7 @@ package Netlists.Gates is
Id_Dyn_Insert : constant Module_Id := 70;
-- OUT := IN0 * STEP, IN0 < MAX
- Id_Memidx1 : constant Module_Id := 71;
+ Id_Memidx : constant Module_Id := 71;
-- OUT := IN0 + IN1, size extension.
Id_Addidx : constant Module_Id := 72;
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index d5a309291..545f6ba62 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -969,8 +969,8 @@ package body Synth.Expr is
Off := Index_To_Offset (Bnd, Idx_Val.Scal, Name) * W;
else
Voff := Dyn_Index_To_Offset (Bnd, Idx_Val, Name);
- Voff := Build_Memidx1 (Get_Build (Syn_Inst), Voff, W, Bnd.Len,
- Width (Clog2 (Uns64 (W * Bnd.Len))));
+ Voff := Build_Memidx (Get_Build (Syn_Inst), Voff, W, Bnd.Len,
+ Width (Clog2 (Uns64 (W * Bnd.Len))));
Off := 0;
end if;
end Synth_Indexed_Name;
@@ -1262,7 +1262,7 @@ package body Synth.Expr is
Synth_Extract_Dyn_Suffix
(Name, Pfx_Bnd, Get_Net (Left), Get_Net (Right),
Inp, Step, Off, Wd);
- Inp := Build_Memidx1
+ Inp := Build_Memidx
(Get_Build (Syn_Inst),
Inp, Step * El_Wd, 0,
Get_Width (Inp) + Width (Clog2 (Uns64 (Step * El_Wd))));