diff options
-rw-r--r-- | testsuite/synth/issue1064/tb_testrec.vhdl | 20 | ||||
-rw-r--r-- | testsuite/synth/issue1064/testrec.vhdl | 29 | ||||
-rwxr-xr-x | testsuite/synth/issue1064/testsuite.sh | 2 |
3 files changed, 50 insertions, 1 deletions
diff --git a/testsuite/synth/issue1064/tb_testrec.vhdl b/testsuite/synth/issue1064/tb_testrec.vhdl new file mode 100644 index 000000000..04bf98b88 --- /dev/null +++ b/testsuite/synth/issue1064/tb_testrec.vhdl @@ -0,0 +1,20 @@ +entity tb_testrec is +end tb_testrec; + +library ieee; +use ieee.std_logic_1164.all; + +architecture behav of tb_testrec is + signal a : std_logic; + signal b : std_logic; +begin + dut: entity work.testrec + port map (a, b); + + process + begin + wait for 1 ns; + assert b = '0' severity failure; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1064/testrec.vhdl b/testsuite/synth/issue1064/testrec.vhdl new file mode 100644 index 000000000..4ef883131 --- /dev/null +++ b/testsuite/synth/issue1064/testrec.vhdl @@ -0,0 +1,29 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity testrec is + port (i : std_ulogic; + o : out std_ulogic); +end entity testrec; + +architecture behaviour of testrec is + type rec is record + v : std_ulogic; + t : std_ulogic; + end record; + + procedure zot(e: inout rec) is + begin + e.v := '0'; + end; + +begin + execute1_1: process(i) + variable v : rec; + begin + v.v := i; + v.t := i; + zot(v); + o <= v.v; + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue1064/testsuite.sh b/testsuite/synth/issue1064/testsuite.sh index ffd46daf3..c0d948a7a 100755 --- a/testsuite/synth/issue1064/testsuite.sh +++ b/testsuite/synth/issue1064/testsuite.sh @@ -3,7 +3,7 @@ . ../../testenv.sh GHDL_STD_FLAGS=--std=08 -for t in test; do +for t in test testrec; do analyze $t.vhdl tb_$t.vhdl elab_simulate tb_$t clean |