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Diffstat (limited to 'doc/using/Synthesis.rst')
| -rw-r--r-- | doc/using/Synthesis.rst | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/doc/using/Synthesis.rst b/doc/using/Synthesis.rst index e5f9554cc..d3968fe67 100644 --- a/doc/using/Synthesis.rst +++ b/doc/using/Synthesis.rst @@ -87,13 +87,16 @@ In addition to those options, there are some synthesis specific options. $ ghdl --synth --std=08 -gDEPTH=12 [library.]top_unit [arch] -.. option:: --out=<vhdl|raw-vhdl|dot|none|raw|dump> +.. option:: --out=<vhdl|raw-vhdl|verilog|dot|none|raw|dump> * **vhdl** *(default)*: equivalent to ``raw-vhdl``, but the original top-level unit is preserved unmodified, so the synthesized design can be simulated with the same testbench. - * **raw-vhdl**: all statements are converted to a simple VHDL 1993 netlist, for allowing instantiation in other - synthesis tools without modern VHDL support. + * **raw-vhdl**: all statements are converted to a simple VHDL 1993 + netlist, for allowing instantiation in other synthesis tools + without modern VHDL support. + + * **verilog**: generate a verilog netlist. * **dot**: generate a graphviz dot diagram of the netlist AST. |