4 files changed, 279 insertions, 0 deletions
diff --git a/doc/using/UART_srcs/rx/UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/UART_RX_8N1.vhd
new file mode 100644
index 000000000..a7fe757a5
--- /dev/null
+++ b/doc/using/UART_srcs/rx/UART_RX_8N1.vhd
@@ -0,0 +1,150 @@
+-- UART_RX_8N1.vhd
+----------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use ieee.numeric_std.all;
+
+
+entity UART_8N1_RX is
+
+  generic (clk_freq : integer;
+           baudrate : integer);
+  port(
+    clk           : in  std_logic;
+    reset         : in  std_logic;
+    --8bit interface
+    rdata         : out std_logic_vector(7 downto 0);
+    rd            : in  std_logic;
+    rd_en         : out std_logic;
+    --physical wire RX
+    rx            : in  std_logic
+    );
+end UART_8N1_RX;
+
+
+architecture Behavioral of UART_8N1_RX is
+
+  type   state_type is (idle, start, data0, data1, data2, data3, data4,
+   data5, data6, data7, stop);
+  signal state : state_type;
+
+  signal puffer : std_logic_vector (7 downto 0);
+
+--FIFO
+  type RAM is array (0 to 63) of std_logic_vector (7 downto 0);
+
+  signal fifo : RAM ;
+
+  signal nextwrite    : unsigned(5 downto 0);
+  signal nextread     : unsigned(5 downto 0);
+
+  constant tick       : integer := clk_freq/baudrate;
+  signal tick_counter : integer range 0 to (tick+1);
+ 
+
+begin
+  
+  rdata  <= fifo(to_integer(nextread));
+  
+  process (clk)
+  begin
+    if rising_edge(clk) then
+      if rd = '1'  then
+        nextread <= nextread+1;
+      end if;
+      if reset = '1' then 
+        nextread <= (others => '0');
+      end if;			  
+    end if;
+  end process;
+
+ rd_en<= '0' when  nextread=nextwrite else '1';
+ 
+
+  process(clk)
+  begin
+    
+    if (clk'event and clk = '1') then
+      tick_counter <= tick_counter + 1;
+
+      case state is
+        
+        when idle =>
+          tick_counter <= 0;
+          if (rx = '0') then  --check start condtion
+            state <= start;
+          else
+            state <= idle;
+          end if;
+            
+        when start =>
+          if (tick_counter = tick/2) then  --capture in the middle
+            tick_counter <= 0;
+            state        <= data0;
+          end if;
+          
+        when data0 =>
+          if (tick_counter = tick) then
+            puffer (0)   <= rx;
+            tick_counter <= 0;
+            state        <= data1;
+          end if;
+        when data1 =>
+          if (tick_counter = tick) then
+            puffer (1)   <= rx;
+            tick_counter <= 0;
+            state        <= data2;
+          end if;
+        when data2 =>
+          if (tick_counter = tick) then
+            puffer (2)   <= rx;
+            tick_counter <= 0;
+            state        <= data3;
+          end if;
+        when data3 =>
+          if (tick_counter = tick) then
+            puffer(3)    <= rx;
+            tick_counter <= 0;
+            state        <= data4;
+          end if;
+        when data4 =>
+          if (tick_counter = tick) then
+            puffer (4)   <= rx;
+            tick_counter <= 0;
+            state        <= data5;
+          end if;
+        when data5 =>
+          if (tick_counter = tick) then
+            puffer (5)   <= rx;
+            tick_counter <= 0;
+            state        <= data6;
+          end if;
+        when data6 =>
+          if (tick_counter = tick) then
+            puffer (6)   <= rx;
+            tick_counter <= 0;
+            state        <= data7;
+          end if;
+        when data7 =>
+          if (tick_counter = tick) then
+            puffer (7)   <= rx;
+            tick_counter <= 0;
+            state        <= stop;
+          end if;
+        when stop =>
+          if (tick_counter = tick) then
+            fifo(to_integer(nextwrite)) <= puffer;
+            nextwrite                   <= nextwrite+1;
+            tick_counter <= 0;
+            state        <= idle;
+          end if;
+      end case;
+      if reset='1' then
+        state <=idle;
+        nextwrite <= (others => '0');
+      end if;
+    end if;
+
+  end process;
+end Behavioral;
+
diff --git a/doc/using/UART_srcs/rx/makefile b/doc/using/UART_srcs/rx/makefile
new file mode 100644
index 000000000..3546a42ad
--- /dev/null
+++ b/doc/using/UART_srcs/rx/makefile
@@ -0,0 +1,8 @@
+
+all:
+	ghdl -i *.vhd
+	ghdl -m tb_UART_RX_8N1
+	ghdl -r tb_UART_RX_8N1 --stop-time=800us --wave=RX.ghw
+
+view:	
+	gtkwave RX.ghw
diff --git a/doc/using/UART_srcs/rx/sim_RX.png b/doc/using/UART_srcs/rx/sim_RX.png
new file mode 100644
index 000000000..5062d26a3
--- /dev/null
+++ b/doc/using/UART_srcs/rx/sim_RX.png
diff --git a/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd b/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd
new file mode 100644
index 000000000..4fd67c8e7
--- /dev/null
+++ b/doc/using/UART_srcs/rx/tb_UART_RX_8N1.vhd
@@ -0,0 +1,121 @@
+-- tb_UART_RX_8N1.vhd
+----------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity tb_UART_RX_8N1 is
+end tb_UART_RX_8N1;
+
+architecture behavior of tb_UART_RX_8N1 is
+
+  signal board_clk     : std_logic := '0';
+  signal reset         : std_logic := '0';
+  signal rx            : std_logic := '1';
+  signal rd            : std_logic := '0';
+  signal rd_en     : std_logic;
+  signal data          : std_logic_vector (7 downto 0);
+ 
+  procedure tx_char (signal txpin : out std_logic; 
+              txdata : in character; baudrate : in integer) is
+    constant bittime : time := (integer(1000000000.0/real(baudrate))) * 1 ns; 
+    variable c       : std_logic_vector(7 downto 0);
+  begin
+    c     := std_logic_vector(to_unsigned(character'pos(txdata), 8));
+    txpin <= '0';                       -- Startbit
+    wait for bittime;
+    for i in 0 to 7 loop
+      txpin <= c(i);
+      wait for bittime;
+    end loop;
+    txpin <= '1';                       -- Stopbit
+    wait for bittime;
+  end tx_char;
+  --Outputs
+
+component UART_8N1_RX is
+
+  generic (clk_freq : integer;
+           baudrate : integer);
+  port(
+    clk           : in  std_logic;
+    reset         : in  std_logic;
+    --8bit interface
+    rdata         : out std_logic_vector(7 downto 0);
+    rd            : in  std_logic;
+    rd_en         : out std_logic;
+    --physical wire RX
+    rx            : in  std_logic
+    );
+end component;   
+  
+  constant board_clk_period : time := 10 ns;
+  constant board_clk_freq: integer :=100E6;   --100MHz
+  
+begin
+
+  -- Instantiate the Unit Under Test (UUT)
+UART_RX:UART_8N1_RX 
+
+  generic map (
+    clk_freq   => board_clk_freq,
+    baudrate   =>115200)
+  port map(
+    clk           => board_clk,
+    reset         => reset,
+    rdata         => data,
+    rd            => rd,
+    rd_en         => rd_en,
+    --physical wire RX
+    rx            => rx
+    );
+
+  process 
+  begin
+    wait for 80000 ns;
+      tx_char(RX, '$', 115200);
+      tx_char(RX, 'g', 115200); 
+      tx_char(RX, '#', 115200); 
+    wait for 50 us;
+      tx_char(RX, '6', 115200);                         
+      tx_char(RX, '7', 115200); 
+   wait;                       -- will wait forever
+   end process;
+          
+  -- Clock process definitions
+  board_clk_process : process
+  begin
+    board_clk <= '0';
+    wait for board_clk_period/2;
+      board_clk <= '1';
+    wait for board_clk_period/2;
+  end process;
+
+  -- Stimulus process
+  process
+     begin
+         reset <= '1';
+       wait for 100 ns;
+        reset <='0';   
+      wait;
+    end process;
+
+   -- Stimulus process
+   stim_proc : process
+   begin 
+ 
+   loop
+      wait for 200 us;                     
+      wait until rising_edge(board_clk);
+      if rd_en='1' then 
+        rd<= '1';
+      end if;
+      wait until rising_edge(board_clk);
+       rd<= '0';        
+    end loop;
+
+      wait;
+    end process;
+
+   end;