aboutsummaryrefslogtreecommitdiffstats
path: root/pyGHDL/dom/Aggregates.py
diff options
context:
space:
mode:
Diffstat (limited to 'pyGHDL/dom/Aggregates.py')
-rw-r--r--pyGHDL/dom/Aggregates.py16
1 files changed, 8 insertions, 8 deletions
diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 87bc44360..dfaee9a2d 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -9,7 +9,7 @@
# Authors:
# Patrick Lehmann
#
-# Package module: DOM: VHDL design units (e.g. context or package).
+# Package module: DOM: Aggregates.
#
# License:
# ============================================================================
@@ -41,13 +41,13 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
"""
from pydecor import export
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
SimpleAggregateElement as VHDLModel_SimpleAggregateElement,
IndexedAggregateElement as VHDLModel_IndexedAggregateElement,
RangedAggregateElement as VHDLModel_RangedAggregateElement,
NamedAggregateElement as VHDLModel_NamedAggregateElement,
OthersAggregateElement as VHDLModel_OthersAggregateElement,
- Expression,
+ ExpressionUnion,
Symbol,
)
from pyGHDL.libghdl._types import Iir
@@ -59,34 +59,34 @@ __all__ = []
@export
class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
- def __init__(self, node: Iir, expression: Expression):
+ def __init__(self, node: Iir, expression: ExpressionUnion):
super().__init__(expression)
DOMMixin.__init__(self, node)
@export
class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
- def __init__(self, node: Iir, index: Expression, expression: Expression):
+ def __init__(self, node: Iir, index: ExpressionUnion, expression: ExpressionUnion):
super().__init__(index, expression)
DOMMixin.__init__(self, node)
@export
class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
- def __init__(self, node: Iir, rng: Range, expression: Expression):
+ def __init__(self, node: Iir, rng: Range, expression: ExpressionUnion):
super().__init__(rng, expression)
DOMMixin.__init__(self, node)
@export
class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
- def __init__(self, node: Iir, name: Symbol, expression: Expression):
+ def __init__(self, node: Iir, name: Symbol, expression: ExpressionUnion):
super().__init__(name, expression)
DOMMixin.__init__(self, node)
@export
class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
- def __init__(self, node: Iir, expression: Expression):
+ def __init__(self, node: Iir, expression: ExpressionUnion):
super().__init__(expression)
DOMMixin.__init__(self, node)