aboutsummaryrefslogtreecommitdiffstats
path: root/pyGHDL/dom/Expression.py
diff options
context:
space:
mode:
Diffstat (limited to 'pyGHDL/dom/Expression.py')
-rw-r--r--pyGHDL/dom/Expression.py381
1 files changed, 196 insertions, 185 deletions
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index b3256d551..972b86ced 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -30,12 +30,14 @@
#
# SPDX-License-Identifier: GPL-2.0-or-later
# ============================================================================
-from typing import List
+from typing import List, Union
from pydecor import export
from pyGHDL.dom import DOMMixin, DOMException
from pyVHDLModel.VHDLModel import (
+ UnaryExpression as VHDLModel_UnaryExpression,
+ BinaryExpression as VHDLModel_BinaryExpression,
InverseExpression as VHDLModel_InverseExpression,
IdentityExpression as VHDLModel_IdentityExpression,
NegationExpression as VHDLModel_NegationExpression,
@@ -67,23 +69,32 @@ from pyVHDLModel.VHDLModel import (
LessEqualExpression as VHDLModel_LessEqualExpression,
GreaterThanExpression as VHDLModel_GreaterThanExpression,
GreaterEqualExpression as VHDLModel_GreaterEqualExpression,
+ MatchingEqualExpression as VHDLModel_MatchingEqualExpression,
+ MatchingUnequalExpression as VHDLModel_MatchingUnequalExpression,
+ MatchingLessThanExpression as VHDLModel_MatchingLessThanExpression,
+ MatchingLessEqualExpression as VHDLModel_MatchingLessEqualExpression,
+ MatchingGreaterThanExpression as VHDLModel_MatchingGreaterThanExpression,
+ MatchingGreaterEqualExpression as VHDLModel_MatchingGreaterEqualExpression,
ShiftRightLogicExpression as VHDLModel_ShiftRightLogicExpression,
ShiftLeftLogicExpression as VHDLModel_ShiftLeftLogicExpression,
ShiftRightArithmeticExpression as VHDLModel_ShiftRightArithmeticExpression,
ShiftLeftArithmeticExpression as VHDLModel_ShiftLeftArithmeticExpression,
RotateRightExpression as VHDLModel_RotateRightExpression,
RotateLeftExpression as VHDLModel_RotateLeftExpression,
+ SubtypeAllocation as VHDLModel_SubtypeAllocation,
+ QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation,
Aggregate as VHDLModel_Aggregate,
Expression,
AggregateElement,
- SubTypeOrSymbol,
+ SubtypeOrSymbol,
+ Symbol,
)
from pyGHDL.libghdl import utils
from pyGHDL.libghdl._types import Iir
from pyGHDL.libghdl.vhdl import nodes
from pyGHDL.dom._Utils import GetIirKindOfNode
-from pyGHDL.dom.Symbol import EnumerationLiteralSymbol, SimpleSubTypeSymbol
+from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
from pyGHDL.dom.Aggregates import (
OthersAggregateElement,
SimpleAggregateElement,
@@ -96,18 +107,18 @@ from pyGHDL.dom.Aggregates import (
__all__ = []
-class _ParseUnaryExpression:
+class _ParseUnaryExpressionMixin:
@classmethod
- def parse(cls, node: Iir):
+ def parse(cls, node: Iir) -> VHDLModel_UnaryExpression:
from pyGHDL.dom._Translate import GetExpressionFromNode
operand = GetExpressionFromNode(nodes.Get_Operand(node))
return cls(node, operand)
-class _ParseBinaryExpression:
+class _ParseBinaryExpressionMixin:
@classmethod
- def parse(cls, node: Iir):
+ def parse(cls, node: Iir) -> VHDLModel_BinaryExpression:
from pyGHDL.dom._Translate import GetExpressionFromNode
left = GetExpressionFromNode(nodes.Get_Left(node))
@@ -116,53 +127,51 @@ class _ParseBinaryExpression:
@export
-class InverseExpression(VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpression):
+class InverseExpression(
+ VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@export
-class IdentityExpression(VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpression):
+class IdentityExpression(
+ VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@export
-class NegationExpression(VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpression):
+class NegationExpression(
+ VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@export
-class AbsoluteExpression(VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpression):
+class AbsoluteExpression(
+ VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin
+):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@export
class ParenthesisExpression(
- VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpression
+ VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin
):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@classmethod
- def parse(cls, node: Iir):
+ def parse(cls, node: Iir) -> "ParenthesisExpression":
from pyGHDL.dom._Translate import GetExpressionFromNode
operand = GetExpressionFromNode(nodes.Get_Expression(node))
@@ -172,11 +181,9 @@ class ParenthesisExpression(
@export
class TypeConversion(VHDLModel_TypeConversion, DOMMixin):
def __init__(self, node: Iir, operand: Expression):
- super().__init__()
+ super().__init__(operand)
DOMMixin.__init__(self, node)
- self._operand = operand
-
@export
class FunctionCall(VHDLModel_FunctionCall, DOMMixin):
@@ -184,12 +191,12 @@ class FunctionCall(VHDLModel_FunctionCall, DOMMixin):
super().__init__()
DOMMixin.__init__(self, node)
- self._operand = operand
-
class RangeExpression(VHDLModel_RangeExpression, DOMMixin):
@classmethod
- def parse(cls, node: Iir) -> "VHDLModel_RangeExpression":
+ def parse(
+ cls, node: Iir
+ ) -> Union["AscendingRangeExpression", "DescendingRangeExpression"]:
from pyGHDL.dom._Translate import GetExpressionFromNode
direction = nodes.Get_Direction(node)
@@ -205,347 +212,350 @@ class RangeExpression(VHDLModel_RangeExpression, DOMMixin):
@export
class AscendingRangeExpression(VHDLModel_AscendingRangeExpression, DOMMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class AdditionExpression(
- VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class SubtractionExpression(
- VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class ConcatenationExpression(
- VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class MultiplyExpression(
- VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class DivisionExpression(
- VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class RemainderExpression(
- VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class ModuloExpression(VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpression):
+class ModuloExpression(
+ VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class ExponentiationExpression(
- VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpression):
+class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpression):
+class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpression):
+class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpression):
+class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpression):
+class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpression):
+class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
-class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpression):
+class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressionMixin):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class UnequalExpression(
+ VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
-class UnequalExpression(VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpression):
+class LessThanExpression(
+ VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class LessEqualExpression(
+ VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
-class LessThanExpression(
- VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpression
+class GreaterThanExpression(
+ VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class GreaterEqualExpression(
+ VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
-class LessEqualExpression(
- VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpression
+class MatchingEqualExpression(
+ VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class MatchingUnequalExpression(
+ VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
-class GreaterThanExpression(
- VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpression
+class MatchingLessThanExpression(
+ VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class MatchingLessEqualExpression(
+ VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
-class GreaterEqualExpression(
- VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpression
+class MatchingGreaterThanExpression(
+ VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
+
+@export
+class MatchingGreaterEqualExpression(
+ VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
+):
+ def __init__(self, node: Iir, left: Expression, right: Expression):
+ super().__init__(left, right)
+ DOMMixin.__init__(self, node)
@export
class ShiftRightLogicExpression(
- VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class ShiftLeftLogicExpression(
- VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class ShiftRightArithmeticExpression(
- VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class ShiftLeftArithmeticExpression(
- VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class RotateRightExpression(
- VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class RotateLeftExpression(
- VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpression
+ VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin
):
def __init__(self, node: Iir, left: Expression, right: Expression):
- super().__init__()
+ super().__init__(left, right)
DOMMixin.__init__(self, node)
- self._leftOperand = left
- self._rightOperand = right
-
@export
class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin):
- def __init__(self, node: Iir, subType: SubTypeOrSymbol, operand: Expression):
- super().__init__()
+ def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: Expression):
+ super().__init__(subtype, operand)
DOMMixin.__init__(self, node)
- self._subtype = subType
- self._operand = operand
-
@classmethod
- def parse(cls, node: Iir):
+ def parse(cls, node: Iir) -> "QualifiedExpression":
from pyGHDL.dom._Translate import GetExpressionFromNode, GetNameOfNode
typeMarkName = GetNameOfNode(nodes.Get_Type_Mark(node))
- subType = SimpleSubTypeSymbol(typeMarkName)
+ subtype = SimpleSubtypeSymbol(node, typeMarkName)
operand = GetExpressionFromNode(nodes.Get_Expression(node))
- return cls(subType, operand)
+ return cls(node, subtype, operand)
+
+
+@export
+class SubtypeAllocation(VHDLModel_SubtypeAllocation, DOMMixin):
+ def __init__(self, node: Iir, subtype: Symbol):
+ super().__init__(subtype)
+ DOMMixin.__init__(self, node)
+
+ @classmethod
+ def parse(cls, node: Iir) -> "QualifiedExpressionAllocation":
+ from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
+
+ subtype = GetSubtypeIndicationFromNode(node, "allocation", "?")
+
+ return cls(node, subtype)
+
+
+@export
+class QualifiedExpressionAllocation(VHDLModel_QualifiedExpressionAllocation, DOMMixin):
+ def __init__(self, node: Iir, qualifiedExpression: QualifiedExpression):
+ super().__init__(qualifiedExpression)
+ DOMMixin.__init__(self, node)
+
+ @classmethod
+ def parse(cls, node: Iir) -> "QualifiedExpressionAllocation":
+ from pyGHDL.dom._Translate import GetExpressionFromNode
+
+ expression = GetExpressionFromNode(nodes.Get_Expression(node))
+
+ return cls(node, expression)
@export
class Aggregate(VHDLModel_Aggregate, DOMMixin):
def __init__(self, node: Iir, elements: List[AggregateElement]):
- super().__init__()
+ super().__init__(elements)
DOMMixin.__init__(self, node)
- self._elements = elements
-
@classmethod
- def parse(cls, node: Iir):
- from pyGHDL.dom._Translate import GetExpressionFromNode, GetRangeFromNode
+ def parse(cls, node: Iir) -> "Aggregate":
+ from pyGHDL.dom._Translate import (
+ GetExpressionFromNode,
+ GetRangeFromNode,
+ GetNameFromNode,
+ )
choices = []
@@ -563,8 +573,9 @@ class Aggregate(VHDLModel_Aggregate, DOMMixin):
r = GetRangeFromNode(nodes.Get_Choice_Range(item))
choices.append(RangedAggregateElement(item, r, value))
elif kind == nodes.Iir_Kind.Choice_By_Name:
- name = EnumerationLiteralSymbol(nodes.Get_Choice_Name(item))
- choices.append(NamedAggregateElement(item, name, value))
+ name = GetNameFromNode(nodes.Get_Choice_Name(item))
+ symbol = Symbol(item, name)
+ choices.append(NamedAggregateElement(item, symbol, value))
elif kind == nodes.Iir_Kind.Choice_By_Others:
choices.append(OthersAggregateElement(item, value))
else:
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 10:13:16 +0000