diff options
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 9539645e3..33501a536 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -358,6 +358,7 @@ package body Simul.Vhdl_Elab is Assoc_Inter : Node; Assoc : Node; Inter : Node; + Formal : Node; Formal_Base : Valtyp; Actual_Base : Valtyp; Formal_Sig : Signal_Index_Type; @@ -375,11 +376,16 @@ package body Simul.Vhdl_Elab is case Get_Kind (Assoc) is when Iir_Kind_Association_Element_By_Name => Inter := Get_Association_Interface (Assoc, Assoc_Inter); + Formal := Get_Formal (Assoc); + if Formal = Null_Iir then + Formal := Inter; + end if; Synth_Assignment_Prefix - (Port_Inst, Inter, Formal_Base, Typ, Off, Dyn); + (Port_Inst, Formal, Formal_Base, Typ, Off, Dyn); pragma Assert (Dyn = No_Dyn_Name); Formal_Sig := Formal_Base.Val.S; Formal_Ep := (Formal_Sig, Off, Typ); + Synth_Assignment_Prefix (Assoc_Inst, Get_Actual (Assoc), Actual_Base, Typ, Off, Dyn); pragma Assert (Dyn = No_Dyn_Name); @@ -416,7 +422,6 @@ package body Simul.Vhdl_Elab is raise Internal_Error; end case; - Connect_Table.Append (Conn); Signals_Table.Table (Formal_Sig).Connect := Connect_Table.Last; |