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-rw-r--r--src/simul/simul-vhdl_simul.adb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb
index 7d1a4312a..c03da08f1 100644
--- a/src/simul/simul-vhdl_simul.adb
+++ b/src/simul/simul-vhdl_simul.adb
@@ -4128,8 +4128,12 @@ package body Simul.Vhdl_Simul is
pragma Assert (Areapools.Is_Empty (Expr_Pool));
pragma Assert (Areapools.Is_Empty (Process_Pool));
+ -- Copy flag.
Synth.Flags.Severity_Level := Grt.Options.Severity_Level;
+ -- Not supported.
+ Grt.Options.Trace_Signals := False;
+
if Flag_Interractive then
Elab.Debugger.Debug_Elab (Vhdl_Elab.Top_Instance);
end if;