diff options
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index db3e82414..710c04814 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -728,10 +728,12 @@ package Std_Names is Name_Rotate_Left : constant Name_Id := Name_First_Ieee + 026; Name_Rotate_Right : constant Name_Id := Name_First_Ieee + 027; Name_To_Bitvector : constant Name_Id := Name_First_Ieee + 028; - Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 029; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 030; - Name_Ceil : constant Name_Id := Name_First_Ieee + 031; - Name_Log2 : constant Name_Id := Name_First_Ieee + 032; + Name_Conv_Signed : constant Name_Id := Name_First_Ieee + 029; + Name_Conv_Unsigned : constant Name_Id := Name_First_Ieee + 030; + Name_Conv_Integer : constant Name_Id := Name_First_Ieee + 031; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 032; + Name_Ceil : constant Name_Id := Name_First_Ieee + 033; + Name_Log2 : constant Name_Id := Name_First_Ieee + 034; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. |