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-rw-r--r--src/synth/netlists-disp_verilog.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb
index cd13a6d77..7d1354403 100644
--- a/src/synth/netlists-disp_verilog.adb
+++ b/src/synth/netlists-disp_verilog.adb
@@ -854,7 +854,7 @@ package body Netlists.Disp_Verilog is
when Id_Neg =>
Disp_Template (" assign \o0 = -\i0;" & NL, Inst);
when Id_Abs=>
- Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst);
+ Disp_Template (" \o0 <= \si0 >= 0 ? \i0 : -\i0;" & NL, Inst);
when Id_Extract =>
Disp_Template (" assign \o0 = ", Inst);
Disp_Extract (Inst);