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-rw-r--r--src/synth/netlists-disp_vhdl.adb17
1 files changed, 10 insertions, 7 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index eae711c57..ac077f4a7 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -645,16 +645,17 @@ package body Netlists.Disp_Vhdl is
-- Clock
S := Get_Input_Net (Port_Inst, 2);
Data_W := Get_Width (Get_Output (Port_Inst, 1));
+ when Id_Memory
+ | Id_Memory_Init =>
+ exit;
when others =>
raise Internal_Error;
end case;
- Disp_Net_Name (S);
- Port := Get_Output (Port_Inst, 0);
- if Is_Connected (Port) then
+ if Port /= Ports then
Put (", ");
- else
- exit;
end if;
+ Disp_Net_Name (S);
+ Port := Get_Output (Port_Inst, 0);
end loop;
Put_Line (") is");
@@ -675,7 +676,7 @@ package body Netlists.Disp_Vhdl is
Val : Net;
Val_Inst : Instance;
begin
- Val := Get_Input_Net (Mem, 0);
+ Val := Get_Input_Net (Mem, 1);
Val_Inst := Get_Net_Parent (Val);
if Get_Id (Val_Inst) = Id_Isignal then
Val := Get_Input_Net (Val_Inst, 1);
@@ -711,11 +712,13 @@ package body Netlists.Disp_Vhdl is
Disp_Template ("\o0", Mem);
Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst);
Put_Line (" end if;");
+ when Id_Memory
+ | Id_Memory_Init =>
+ exit;
when others =>
raise Internal_Error;
end case;
Port := Get_Output (Port_Inst, 0);
- exit when not Is_Connected (Port);
end loop;
Put_Line (" end process;");
end Disp_Memory;