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Diffstat (limited to 'src/vhdl/simulate/simulation.adb')
| -rw-r--r-- | src/vhdl/simulate/simulation.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index b02d47dd2..c33997b7d 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -1112,6 +1112,9 @@ package body Simulation is Release (Marker, Expr_Pool); if V then Nvec := (others => False); + if Get_Kind (E.Stmt) = Iir_Kind_Psl_Cover_Statement then + Nvec (0) := True; + end if; -- For each state: if set, evaluate all outgoing edges. NFA := Get_PSL_NFA (E.Stmt); |