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| author | Tristan Gingold <tgingold@free.fr> | 2016-02-13 18:00:36 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-02-14 13:52:34 +0100 |
| commit | ace70f3cc4d5ac8d5fb7e02e96d5b3187319e520 (patch) | |
| tree | 775665dcf6ac26054734e1cc9a543bbc8f2281b9 /src/vhdl/simulate/simulation.adb | |
| parent | 2c88f7c0f5a9859eeb118147444afbd47c71c2a8 (diff) | |
| download | ghdl-ace70f3cc4d5ac8d5fb7e02e96d5b3187319e520.tar.gz ghdl-ace70f3cc4d5ac8d5fb7e02e96d5b3187319e520.tar.bz2 ghdl-ace70f3cc4d5ac8d5fb7e02e96d5b3187319e520.zip | |
psl: cover directive works on a sequence, not on a property.
Diffstat (limited to 'src/vhdl/simulate/simulation.adb')
| -rw-r--r-- | src/vhdl/simulate/simulation.adb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb index b02d47dd2..c33997b7d 100644 --- a/src/vhdl/simulate/simulation.adb +++ b/src/vhdl/simulate/simulation.adb @@ -1112,6 +1112,9 @@ package body Simulation is Release (Marker, Expr_Pool); if V then Nvec := (others => False); + if Get_Kind (E.Stmt) = Iir_Kind_Psl_Cover_Statement then + Nvec (0) := True; + end if; -- For each state: if set, evaluate all outgoing edges. NFA := Get_PSL_NFA (E.Stmt); |