3 files changed, 11 insertions, 11 deletions
diff --git a/src/vhdl/simulate/simul-debugger.adb b/src/vhdl/simulate/simul-debugger.adb
index 10789cb25..8c911a706 100644
--- a/src/vhdl/simulate/simul-debugger.adb
+++ b/src/vhdl/simulate/simul-debugger.adb
@@ -26,8 +26,8 @@ with Files_Map;
 with Vhdl.Parse;
 with Vhdl.Scanner;
 with Vhdl.Tokens;
-with Sem_Expr;
-with Sem_Scopes;
+with Vhdl.Sem_Expr;
+with Vhdl.Sem_Scopes;
 with Vhdl.Canon;
 with Std_Names;
 with Libraries;
@@ -1750,7 +1750,7 @@ package body Simul.Debugger is
 
    procedure Add_Decls_For (N : Iir)
    is
-      use Sem_Scopes;
+      use Vhdl.Sem_Scopes;
    begin
       case Get_Kind (N) is
          when Iir_Kind_Entity_Declaration =>
@@ -1819,7 +1819,7 @@ package body Simul.Debugger is
 
    procedure Enter_Scope (Node : Iir)
    is
-      use Sem_Scopes;
+      use Vhdl.Sem_Scopes;
    begin
       Push_Interpretations;
       Open_Declarative_Region;
@@ -1833,7 +1833,7 @@ package body Simul.Debugger is
 
    procedure Del_Decls_For (N : Iir)
    is
-      use Sem_Scopes;
+      use Vhdl.Sem_Scopes;
    begin
       case Get_Kind (N) is
          when Iir_Kind_Entity_Declaration =>
@@ -1858,7 +1858,7 @@ package body Simul.Debugger is
 
    procedure Leave_Scope (Node : Iir)
    is
-      use Sem_Scopes;
+      use Vhdl.Sem_Scopes;
    begin
       Foreach_Scopes (Node, Del_Decls_For'Access);
 
@@ -1914,7 +1914,7 @@ package body Simul.Debugger is
       end if;
 
       Enter_Scope (Dbg_Cur_Frame.Stmt);
-      Expr := Sem_Expr.Sem_Expression_Universal (Expr);
+      Expr := Vhdl.Sem_Expr.Sem_Expression_Universal (Expr);
       Leave_Scope (Dbg_Cur_Frame.Stmt);
 
       if Expr = Null_Iir
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index cb9c8cb9b..3addbef91 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -26,7 +26,7 @@ with Libraries;
 with Name_Table;
 with Simul.File_Operation;
 with Iir_Chains; use Iir_Chains;
-with Sem_Lib; use Sem_Lib;
+with Vhdl.Sem_Lib; use Vhdl.Sem_Lib;
 with Simul.Annotations; use Simul.Annotations;
 with Simul.Elaboration.AMS; use Simul.Elaboration.AMS;
 with Areapools; use Areapools;
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb
index f034bb9b6..3a1c11028 100644
--- a/src/vhdl/simulate/simul-execution.adb
+++ b/src/vhdl/simulate/simul-execution.adb
@@ -44,7 +44,7 @@ with Grt.Errors;
 with Grt.Std_Logic_1164;
 with Grt.Lib;
 with Grt.Strings;
-with Sem_Inst;
+with Vhdl.Sem_Inst;
 
 package body Simul.Execution is
 
@@ -3344,7 +3344,7 @@ package body Simul.Execution is
       if Res /= Null_Iir then
          return Res;
       else
-         Orig := Sem_Inst.Get_Origin (Spec);
+         Orig := Vhdl.Sem_Inst.Get_Origin (Spec);
          pragma Assert (Orig /= Null_Iir);
          return Get_Subprogram_Body_Origin (Orig);
       end if;
@@ -3361,7 +3361,7 @@ package body Simul.Execution is
       if Res /= Null_Iir then
          return Res;
       else
-         Orig := Sem_Inst.Get_Origin (Spec);
+         Orig := Vhdl.Sem_Inst.Get_Origin (Spec);
          return Get_Protected_Type_Body_Origin (Orig);
       end if;
    end Get_Protected_Type_Body_Origin;