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-rw-r--r--src/vhdl/vhdl-errors.adb66
1 files changed, 62 insertions, 4 deletions
diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb
index ad57a735c..8cdbec4ab 100644
--- a/src/vhdl/vhdl-errors.adb
+++ b/src/vhdl/vhdl-errors.adb
@@ -216,6 +216,19 @@ package body Vhdl.Errors is
end if;
end Disp_Type;
+ function Disp_Nature (Node : Iir; Str : String) return String
+ is
+ Decl: Iir;
+ begin
+ Decl := Get_Nature_Declarator (Node);
+ if Decl = Null_Iir then
+ return "anonymous " & Str
+ & " defined at " & Disp_Location (Node);
+ else
+ return Disp_Identifier (Decl, Str);
+ end if;
+ end Disp_Nature;
+
begin
case Get_Kind (Node) is
when Iir_Kind_String_Literal8 =>
@@ -231,7 +244,8 @@ package body Vhdl.Errors is
return "physical literal";
when Iir_Kind_Enumeration_Literal =>
return "enumeration literal " & Image_Identifier (Node);
- when Iir_Kind_Element_Declaration =>
+ when Iir_Kind_Element_Declaration
+ | Iir_Kind_Nature_Element_Declaration =>
return Disp_Identifier (Node, "element");
when Iir_Kind_Record_Element_Constraint =>
return "record element constraint";
@@ -273,7 +287,8 @@ package body Vhdl.Errors is
when Iir_Kind_Association_Element_By_Expression
| Iir_Kind_Association_Element_Package
| Iir_Kind_Association_Element_Type
- | Iir_Kind_Association_Element_Subprogram =>
+ | Iir_Kind_Association_Element_Subprogram
+ | Iir_Kind_Association_Element_Terminal =>
return "association element";
when Iir_Kind_Overload_List =>
return "overloaded name or expression";
@@ -320,7 +335,13 @@ package body Vhdl.Errors is
return "subtype definition";
when Iir_Kind_Scalar_Nature_Definition =>
- return Image_Identifier (Get_Nature_Declarator (Node));
+ return Disp_Nature (Node, "scalar nature");
+ when Iir_Kind_Array_Nature_Definition =>
+ return Disp_Nature (Node, "array nature");
+ when Iir_Kind_Array_Subnature_Definition =>
+ return Disp_Nature (Node, "array subnature");
+ when Iir_Kind_Record_Nature_Definition =>
+ return Disp_Nature (Node, "record nature");
when Iir_Kind_Choice_By_Expression =>
return "choice by expression";
@@ -408,6 +429,8 @@ package body Vhdl.Errors is
return ".all name";
when Iir_Kind_Psl_Expression =>
return "PSL instantiation";
+ when Iir_Kind_Break_Element =>
+ return "break element";
when Iir_Kind_Interface_Constant_Declaration =>
if Get_Parent (Node) = Null_Iir then
@@ -435,6 +458,10 @@ package body Vhdl.Errors is
return Disp_Identifier (Node, "variable interface");
when Iir_Kind_Interface_File_Declaration =>
return Disp_Identifier (Node, "file interface");
+ when Iir_Kind_Interface_Quantity_Declaration =>
+ return Disp_Identifier (Node, "quantity interface");
+ when Iir_Kind_Interface_Terminal_Declaration =>
+ return Disp_Identifier (Node, "terminal interface");
when Iir_Kind_Interface_Package_Declaration =>
return Disp_Identifier (Node, "package interface");
when Iir_Kind_Interface_Type_Declaration =>
@@ -535,6 +562,8 @@ package body Vhdl.Errors is
return "context reference";
when Iir_Kind_Disconnection_Specification =>
return "disconnection specification";
+ when Iir_Kind_Step_Limit_Specification =>
+ return "step limit specification";
when Iir_Kind_Slice_Name =>
return "slice";
@@ -573,6 +602,11 @@ package body Vhdl.Errors is
when Iir_Kind_Simple_Simultaneous_Statement =>
return "simple simultaneous statement";
+ when Iir_Kind_Simultaneous_Procedural_Statement =>
+ return "simultaneous procedural statement";
+ when Iir_Kind_Simultaneous_If_Statement
+ | Iir_Kind_Simultaneous_Elsif =>
+ return "simultaneous if statement";
when Iir_Kind_Psl_Declaration =>
return Disp_Identifier (Node, "PSL declaration");
@@ -583,7 +617,9 @@ package body Vhdl.Errors is
return Disp_Identifier (Node, "terminal declaration");
when Iir_Kind_Free_Quantity_Declaration
| Iir_Kind_Across_Quantity_Declaration
- | Iir_Kind_Through_Quantity_Declaration =>
+ | Iir_Kind_Through_Quantity_Declaration
+ | Iir_Kind_Spectrum_Quantity_Declaration
+ | Iir_Kind_Noise_Quantity_Declaration =>
return Disp_Identifier (Node, "quantity declaration");
when Iir_Kind_Attribute_Declaration =>
@@ -598,6 +634,12 @@ package body Vhdl.Errors is
return "attribute";
when Iir_Kind_Base_Attribute =>
return "'base attribute";
+ when Iir_Kind_Across_Attribute =>
+ return "'across attribute";
+ when Iir_Kind_Through_Attribute =>
+ return "'through attribute";
+ when Iir_Kind_Nature_Reference_Attribute =>
+ return "'reference attribute";
when Iir_Kind_Length_Array_Attribute =>
return "'length attribute";
when Iir_Kind_Range_Array_Attribute =>
@@ -639,6 +681,17 @@ package body Vhdl.Errors is
when Iir_Kind_High_Type_Attribute
| Iir_Kind_High_Array_Attribute =>
return "'high attribute";
+ when Iir_Kind_Signal_Slew_Attribute
+ | Iir_Kind_Quantity_Slew_Attribute =>
+ return "'slew attribute";
+ when Iir_Kind_Ramp_Attribute =>
+ return "'ramp attribute";
+ when Iir_Kind_Dot_Attribute =>
+ return "'dot attribute";
+ when Iir_Kind_Integ_Attribute =>
+ return "'integ attribute";
+ when Iir_Kind_Above_Attribute =>
+ return "'above attribute";
when Iir_Kind_Transaction_Attribute =>
return "'transaction attribute";
when Iir_Kind_Stable_Attribute =>
@@ -695,6 +748,9 @@ package body Vhdl.Errors is
(Node, "concurrent selected signal assignment");
when Iir_Kind_Concurrent_Assertion_Statement =>
return Disp_Label (Node, "concurrent assertion");
+ when Iir_Kind_Concurrent_Break_Statement =>
+ return Disp_Label (Node, "concurrent break statement");
+
when Iir_Kind_Psl_Assert_Directive =>
return Disp_Label (Node, "PSL assertion");
when Iir_Kind_Psl_Assume_Directive =>
@@ -739,6 +795,8 @@ package body Vhdl.Errors is
return Disp_Label (Node, "assertion statement");
when Iir_Kind_Report_Statement =>
return Disp_Label (Node, "report statement");
+ when Iir_Kind_Break_Statement =>
+ return Disp_Label (Node, "break statement");
when Iir_Kind_Block_Configuration =>
return "block configuration";