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-rw-r--r--src/vhdl/vhdl-ieee-std_logic_arith.adb8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb
index 0786f753e..b3f6e9c81 100644
--- a/src/vhdl/vhdl-ieee-std_logic_arith.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb
@@ -50,6 +50,12 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log);
+ Conv_Sgn_Patterns : constant Conv_Pattern_Type :=
+ (Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Sgn,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Uns,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Int,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Log);
+
Conv_Int_Patterns : constant Conv_Pattern_Type :=
(Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Sgn,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Integer_Uns,
@@ -521,6 +527,8 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Def := Handle_Bin (Mul_Patterns);
when Name_Conv_Unsigned =>
Def := Handle_Conv (Conv_Uns_Patterns);
+ when Name_Conv_Signed =>
+ Def := Handle_Conv (Conv_Sgn_Patterns);
when Name_Conv_Std_Logic_Vector =>
Def := Handle_Conv (Conv_Vec_Patterns);
when Name_Op_Less =>