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-rw-r--r--src/vhdl/simulate/simul-simulation-main.adb4
-rw-r--r--src/vhdl/translate/ortho_front.adb6
-rw-r--r--src/vhdl/translate/trans-chap9.adb4
-rw-r--r--src/vhdl/vhdl-ieee-numeric.adb (renamed from src/vhdl/ieee-numeric.adb)6
-rw-r--r--src/vhdl/vhdl-ieee-numeric.ads (renamed from src/vhdl/ieee-numeric.ads)4
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.adb (renamed from src/vhdl/ieee-std_logic_1164.adb)4
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.ads (renamed from src/vhdl/ieee-std_logic_1164.ads)4
-rw-r--r--src/vhdl/vhdl-ieee-vital_timing.adb (renamed from src/vhdl/ieee-vital_timing.adb)6
-rw-r--r--src/vhdl/vhdl-ieee-vital_timing.ads (renamed from src/vhdl/ieee-vital_timing.ads)4
-rw-r--r--src/vhdl/vhdl-ieee.adb (renamed from src/vhdl/ieee.adb)4
-rw-r--r--src/vhdl/vhdl-ieee.ads (renamed from src/vhdl/ieee.ads)4
-rw-r--r--src/vhdl/vhdl-post_sems.adb21
-rw-r--r--src/vhdl/vhdl-sem.adb4
-rw-r--r--src/vhdl/vhdl-sem_psl.adb4
-rw-r--r--src/vhdl/vhdl-sem_types.adb6
-rw-r--r--src/vhdl/vhdl-sem_utils.adb2
16 files changed, 44 insertions, 43 deletions
diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb
index 2d0558308..141e1fd2d 100644
--- a/src/vhdl/simulate/simul-simulation-main.adb
+++ b/src/vhdl/simulate/simul-simulation-main.adb
@@ -29,7 +29,7 @@ with Trans_Analyzes;
with Simul.Elaboration; use Simul.Elaboration;
with Simul.Execution; use Simul.Execution;
with Simul.Annotations; use Simul.Annotations;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Grt.Main;
with Simul.Debugger; use Simul.Debugger;
with Simul.Debugger.AMS;
@@ -381,7 +381,7 @@ package body Simul.Simulation.Main is
Res := Execute_Expression (Instance, E);
if Rtype = Vhdl.Std_Package.Boolean_Type_Definition then
return Res.B1 = True;
- elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then
+ elsif Rtype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then
return Res.E8 = 3 or Res.E8 = 7; -- 1 or H
else
Error_Kind ("execute_psl_expr", Expr);
diff --git a/src/vhdl/translate/ortho_front.adb b/src/vhdl/translate/ortho_front.adb
index 6db015494..2ce7a34a4 100644
--- a/src/vhdl/translate/ortho_front.adb
+++ b/src/vhdl/translate/ortho_front.adb
@@ -25,7 +25,7 @@ with Interning;
with Iirs; use Iirs;
with Libraries;
with Iirs_Utils; use Iirs_Utils;
-with Std_Package;
+with Vhdl.Std_Package;
with Flags;
with Vhdl.Configuration;
with Translation;
@@ -327,8 +327,8 @@ package body Ortho_Front is
Vhdl.Configuration.Flag_Load_All_Design_Units := False;
-- Exclude std.standard
- Set_Configuration_Mark_Flag (Std_Package.Std_Standard_Unit, True);
- Set_Configuration_Done_Flag (Std_Package.Std_Standard_Unit, True);
+ Set_Configuration_Mark_Flag (Vhdl.Std_Package.Std_Standard_Unit, True);
+ Set_Configuration_Done_Flag (Vhdl.Std_Package.Std_Standard_Unit, True);
Dep_List := Create_Iir_List;
diff --git a/src/vhdl/translate/trans-chap9.adb b/src/vhdl/translate/trans-chap9.adb
index 0bf153ebf..f4dc4a422 100644
--- a/src/vhdl/translate/trans-chap9.adb
+++ b/src/vhdl/translate/trans-chap9.adb
@@ -27,7 +27,7 @@ with Nodes_Meta;
with PSL.Nodes;
with PSL.NFAs;
with PSL.NFAs.Utils;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Trans.Chap1;
with Trans.Chap3;
with Trans.Chap4;
@@ -389,7 +389,7 @@ package body Trans.Chap9 is
Res,
New_Lit (Get_Ortho_Literal (Bit_1)),
Get_Ortho_Type (Boolean_Type_Definition, Mode_Value));
- elsif Rtype = Ieee.Std_Logic_1164.Std_Ulogic_Type then
+ elsif Rtype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type then
return New_Value
(New_Indexed_Element
(New_Obj (Ghdl_Std_Ulogic_To_Boolean_Array),
diff --git a/src/vhdl/ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index c6dfcb17a..49f1ee4fb 100644
--- a/src/vhdl/ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -20,9 +20,9 @@ with Types; use Types;
with Vhdl.Std_Package;
with Std_Names; use Std_Names;
with Errorout; use Errorout;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
-package body Ieee.Numeric is
+package body Vhdl.Ieee.Numeric is
type Pkg_Kind is (Pkg_Std, Pkg_Bit);
type Sign_Kind is (Type_Signed, Type_Unsigned,
Type_Log, Type_Slv, Type_Suv);
@@ -256,4 +256,4 @@ package body Ieee.Numeric is
Numeric_Std_Unsigned_Type := Null_Iir;
Numeric_Std_Signed_Type := Null_Iir;
end Extract_Std_Declarations;
-end Ieee.Numeric;
+end Vhdl.Ieee.Numeric;
diff --git a/src/vhdl/ieee-numeric.ads b/src/vhdl/vhdl-ieee-numeric.ads
index 04213bea7..873cb8370 100644
--- a/src/vhdl/ieee-numeric.ads
+++ b/src/vhdl/vhdl-ieee-numeric.ads
@@ -16,11 +16,11 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
-package Ieee.Numeric is
+package Vhdl.Ieee.Numeric is
Numeric_Std_Pkg : Iir_Package_Declaration := Null_Iir;
Numeric_Std_Unsigned_Type : Iir_Array_Type_Definition := Null_Iir;
Numeric_Std_Signed_Type : Iir_Array_Type_Definition := Null_Iir;
-- Extract declarations from PKG (ieee.numeric_std).
procedure Extract_Std_Declarations (Pkg : Iir_Package_Declaration);
-end Ieee.Numeric;
+end Vhdl.Ieee.Numeric;
diff --git a/src/vhdl/ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 9d66942f9..6932dc9ef 100644
--- a/src/vhdl/ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -20,7 +20,7 @@ with Name_Table;
with Std_Names; use Std_Names;
with Errorout; use Errorout;
-package body Ieee.Std_Logic_1164 is
+package body Vhdl.Ieee.Std_Logic_1164 is
function Is_Scalar_Parameter (Inter : Iir) return Boolean is
begin
return Get_Base_Type (Get_Type (Inter)) = Std_Ulogic_Type;
@@ -316,4 +316,4 @@ package body Ieee.Std_Logic_1164 is
Rising_Edge := Null_Iir;
Falling_Edge := Null_Iir;
end Extract_Declarations;
-end Ieee.Std_Logic_1164;
+end Vhdl.Ieee.Std_Logic_1164;
diff --git a/src/vhdl/ieee-std_logic_1164.ads b/src/vhdl/vhdl-ieee-std_logic_1164.ads
index 8e2a6846c..f5c92b5f1 100644
--- a/src/vhdl/ieee-std_logic_1164.ads
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.ads
@@ -16,7 +16,7 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
-package Ieee.Std_Logic_1164 is
+package Vhdl.Ieee.Std_Logic_1164 is
-- Nodes corresponding to declarations in the package.
Std_Logic_1164_Pkg : Iir_Package_Declaration := Null_Iir;
Std_Ulogic_Type : Iir_Enumeration_Type_Definition := Null_Iir;
@@ -44,4 +44,4 @@ package Ieee.Std_Logic_1164 is
-- PKG is the package declaration for ieee.std_logic_1164 package.
-- Fills the node aboves.
procedure Extract_Declarations (Pkg : Iir_Package_Declaration);
-end Ieee.Std_Logic_1164;
+end Vhdl.Ieee.Std_Logic_1164;
diff --git a/src/vhdl/ieee-vital_timing.adb b/src/vhdl/vhdl-ieee-vital_timing.adb
index d4777d651..3a343858f 100644
--- a/src/vhdl/ieee-vital_timing.adb
+++ b/src/vhdl/vhdl-ieee-vital_timing.adb
@@ -21,14 +21,14 @@ with Errorout; use Errorout;
with Vhdl.Std_Package; use Vhdl.Std_Package;
with Vhdl.Tokens; use Vhdl.Tokens;
with Name_Table;
-with Ieee.Std_Logic_1164; use Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164; use Vhdl.Ieee.Std_Logic_1164;
with Vhdl.Sem_Scopes;
with Vhdl.Sem_Specs;
with Evaluation;
with Vhdl.Sem;
with Iirs_Utils;
-package body Ieee.Vital_Timing is
+package body Vhdl.Ieee.Vital_Timing is
-- This package is based on IEEE 1076.4 1995.
-- Control generics identifier.
@@ -1352,4 +1352,4 @@ package body Ieee.Vital_Timing is
-- FIXME: todo
end Check_Vital_Level1;
-end Ieee.Vital_Timing;
+end Vhdl.Ieee.Vital_Timing;
diff --git a/src/vhdl/ieee-vital_timing.ads b/src/vhdl/vhdl-ieee-vital_timing.ads
index 59edf35b0..4dbd64bdf 100644
--- a/src/vhdl/ieee-vital_timing.ads
+++ b/src/vhdl/vhdl-ieee-vital_timing.ads
@@ -16,7 +16,7 @@
-- Software Foundation, 59 Temple Place - Suite 330, Boston, MA
-- 02111-1307, USA.
-package Ieee.Vital_Timing is
+package Vhdl.Ieee.Vital_Timing is
-- Attribute declarations.
Vital_Level0_Attribute : Iir_Attribute_Declaration := Null_Iir;
Vital_Level1_Attribute : Iir_Attribute_Declaration := Null_Iir;
@@ -37,4 +37,4 @@ package Ieee.Vital_Timing is
procedure Check_Vital_Level0 (Unit : Iir_Design_Unit);
procedure Check_Vital_Level1 (Unit : Iir_Design_Unit);
-end Ieee.Vital_Timing;
+end Vhdl.Ieee.Vital_Timing;
diff --git a/src/vhdl/ieee.adb b/src/vhdl/vhdl-ieee.adb
index 393a05d32..8d1021efb 100644
--- a/src/vhdl/ieee.adb
+++ b/src/vhdl/vhdl-ieee.adb
@@ -19,7 +19,7 @@
with Iirs_Utils; use Iirs_Utils;
with Vhdl.Std_Package;
-package body Ieee is
+package body Vhdl.Ieee is
function Skip_Copyright_Notice (Decl : Iir) return Iir
is
begin
@@ -47,4 +47,4 @@ package body Ieee is
end loop;
return Res;
end Skip_Implicit;
-end Ieee;
+end Vhdl.Ieee;
diff --git a/src/vhdl/ieee.ads b/src/vhdl/vhdl-ieee.ads
index e29e50f4d..53a094ea7 100644
--- a/src/vhdl/ieee.ads
+++ b/src/vhdl/vhdl-ieee.ads
@@ -17,10 +17,10 @@
-- 02111-1307, USA.
with Iirs; use Iirs;
-package Ieee is
+package Vhdl.Ieee is
-- Skip constant string declaration for a copyright, if present.
function Skip_Copyright_Notice (Decl : Iir) return Iir;
-- Return the next node after implicit subprogram declarations.
function Skip_Implicit (Decl : Iir) return Iir;
-end Ieee;
+end Vhdl.Ieee;
diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb
index 6c653e4fc..4a8c96697 100644
--- a/src/vhdl/vhdl-post_sems.adb
+++ b/src/vhdl/vhdl-post_sems.adb
@@ -18,9 +18,9 @@
with Types; use Types;
with Std_Names; use Std_Names;
with Vhdl.Sem_Specs;
-with Ieee.Std_Logic_1164;
-with Ieee.Vital_Timing;
-with Ieee.Numeric;
+with Vhdl.Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Vital_Timing;
+with Vhdl.Ieee.Numeric;
with Flags; use Flags;
package body Vhdl.Post_Sems is
@@ -51,11 +51,11 @@ package body Vhdl.Post_Sems is
if Get_Kind (Lib_Unit) = Iir_Kind_Package_Declaration then
case Id is
when Name_Std_Logic_1164 =>
- Ieee.Std_Logic_1164.Extract_Declarations (Lib_Unit);
+ Vhdl.Ieee.Std_Logic_1164.Extract_Declarations (Lib_Unit);
when Name_VITAL_Timing =>
- Ieee.Vital_Timing.Extract_Declarations (Lib_Unit);
+ Vhdl.Ieee.Vital_Timing.Extract_Declarations (Lib_Unit);
when Name_Numeric_Std =>
- Ieee.Numeric.Extract_Std_Declarations (Lib_Unit);
+ Vhdl.Ieee.Numeric.Extract_Std_Declarations (Lib_Unit);
when others =>
null;
end case;
@@ -69,10 +69,11 @@ package body Vhdl.Post_Sems is
while Value /= Null_Iir loop
Spec := Get_Attribute_Specification (Value);
Attr_Decl := Get_Named_Entity (Get_Attribute_Designator (Spec));
- if Attr_Decl = Ieee.Vital_Timing.Vital_Level0_Attribute then
- Ieee.Vital_Timing.Check_Vital_Level0 (Unit);
- elsif Attr_Decl = Ieee.Vital_Timing.Vital_Level1_Attribute then
- Ieee.Vital_Timing.Check_Vital_Level1 (Unit);
+ if Attr_Decl = Vhdl.Ieee.Vital_Timing.Vital_Level0_Attribute then
+ Vhdl.Ieee.Vital_Timing.Check_Vital_Level0 (Unit);
+ elsif Attr_Decl = Vhdl.Ieee.Vital_Timing.Vital_Level1_Attribute
+ then
+ Vhdl.Ieee.Vital_Timing.Check_Vital_Level1 (Unit);
end if;
Value := Get_Value_Chain (Value);
diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb
index 878713ce6..0af9db861 100644
--- a/src/vhdl/vhdl-sem.adb
+++ b/src/vhdl/vhdl-sem.adb
@@ -17,7 +17,7 @@
-- 02111-1307, USA.
with Errorout; use Errorout;
with Vhdl.Std_Package; use Vhdl.Std_Package;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Libraries;
with Std_Names;
with Vhdl.Sem_Scopes; use Vhdl.Sem_Scopes;
@@ -2661,7 +2661,7 @@ package body Vhdl.Sem is
and then (Get_Identifier (Get_Library (Get_Design_File (Unit)))
= Std_Names.Name_Ieee)
then
- Ieee.Std_Logic_1164.Std_Logic_1164_Pkg := Pkg;
+ Vhdl.Ieee.Std_Logic_1164.Std_Logic_1164_Pkg := Pkg;
end if;
-- LRM93 10.1 Declarative Region
diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb
index a528da0be..fb812706a 100644
--- a/src/vhdl/vhdl-sem_psl.adb
+++ b/src/vhdl/vhdl-sem_psl.adb
@@ -29,7 +29,7 @@ with Std_Names;
with Iirs_Utils; use Iirs_Utils;
with Evaluation; use Evaluation;
with Vhdl.Std_Package;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Errorout; use Errorout;
with Xrefs; use Xrefs;
@@ -48,7 +48,7 @@ package body Vhdl.Sem_Psl is
Btype := Get_Base_Type (Atype);
return Btype = Vhdl.Std_Package.Boolean_Type_Definition
or else Btype = Vhdl.Std_Package.Bit_Type_Definition
- or else Btype = Ieee.Std_Logic_1164.Std_Ulogic_Type;
+ or else Btype = Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type;
end Is_Psl_Bool_Type;
-- Return TRUE if EXPR type is a PSL boolean type.
diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb
index f56ba309b..7f2bcd6aa 100644
--- a/src/vhdl/vhdl-sem_types.adb
+++ b/src/vhdl/vhdl-sem_types.adb
@@ -30,7 +30,7 @@ with Name_Table;
with Std_Names;
with Iirs_Utils; use Iirs_Utils;
with Vhdl.Std_Package; use Vhdl.Std_Package;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Xrefs; use Xrefs;
package body Vhdl.Sem_Types is
@@ -837,9 +837,9 @@ package body Vhdl.Sem_Types is
-- Identifier IEEE.Std_Logic_1164.Std_Ulogic.
if Get_Identifier (Decl) = Std_Names.Name_Std_Ulogic
and then
- Get_Parent (Decl) = Ieee.Std_Logic_1164.Std_Logic_1164_Pkg
+ Get_Parent (Decl) = Vhdl.Ieee.Std_Logic_1164.Std_Logic_1164_Pkg
then
- Ieee.Std_Logic_1164.Std_Ulogic_Type := Def;
+ Vhdl.Ieee.Std_Logic_1164.Std_Ulogic_Type := Def;
end if;
return Def;
diff --git a/src/vhdl/vhdl-sem_utils.adb b/src/vhdl/vhdl-sem_utils.adb
index a82628dde..11585bb90 100644
--- a/src/vhdl/vhdl-sem_utils.adb
+++ b/src/vhdl/vhdl-sem_utils.adb
@@ -21,7 +21,7 @@ with Flags; use Flags;
with Errorout; use Errorout;
with Iirs_Utils; use Iirs_Utils;
with Iir_Chains; use Iir_Chains;
-with Ieee.Std_Logic_1164;
+with Vhdl.Ieee.Std_Logic_1164;
with Std_Names;
with Vhdl.Std_Package; use Vhdl.Std_Package;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-08 15:00:46 +0000