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-rw-r--r--testsuite/gna/issue818/tc1.vhdl17
-rw-r--r--testsuite/gna/issue818/tc10.vhdl17
-rw-r--r--testsuite/gna/issue818/tc11.vhdl17
-rw-r--r--testsuite/gna/issue818/tc12.vhdl17
-rw-r--r--testsuite/gna/issue818/tc13.vhdl17
-rw-r--r--testsuite/gna/issue818/tc14.vhdl17
-rw-r--r--testsuite/gna/issue818/tc15.vhdl17
-rw-r--r--testsuite/gna/issue818/tc16.vhdl17
-rw-r--r--testsuite/gna/issue818/tc17.vhdl17
-rw-r--r--testsuite/gna/issue818/tc2.vhdl17
-rw-r--r--testsuite/gna/issue818/tc3.vhdl17
-rw-r--r--testsuite/gna/issue818/tc4.vhdl17
-rw-r--r--testsuite/gna/issue818/tc5.vhdl17
-rw-r--r--testsuite/gna/issue818/tc6.vhdl17
-rw-r--r--testsuite/gna/issue818/tc7.vhdl17
-rw-r--r--testsuite/gna/issue818/tc8.vhdl17
-rw-r--r--testsuite/gna/issue818/tc9.vhdl17
-rwxr-xr-xtestsuite/gna/issue818/testsuite.sh39
18 files changed, 328 insertions, 0 deletions
diff --git a/testsuite/gna/issue818/tc1.vhdl b/testsuite/gna/issue818/tc1.vhdl
new file mode 100644
index 000000000..ff2cc0775
--- /dev/null
+++ b/testsuite/gna/issue818/tc1.vhdl
@@ -0,0 +1,17 @@
+entity tc1 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc1 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc10.vhdl b/testsuite/gna/issue818/tc10.vhdl
new file mode 100644
index 000000000..5af0acff5
--- /dev/null
+++ b/testsuite/gna/issue818/tc10.vhdl
@@ -0,0 +1,17 @@
+entity tc10 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc10 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? falling_edge(clk) and (?? tg) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc11.vhdl b/testsuite/gna/issue818/tc11.vhdl
new file mode 100644
index 000000000..9ba6d036f
--- /dev/null
+++ b/testsuite/gna/issue818/tc11.vhdl
@@ -0,0 +1,17 @@
+entity tc11 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc11 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if (tg) and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc12.vhdl b/testsuite/gna/issue818/tc12.vhdl
new file mode 100644
index 000000000..bbd667b3d
--- /dev/null
+++ b/testsuite/gna/issue818/tc12.vhdl
@@ -0,0 +1,17 @@
+entity tc12 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc12 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if tg and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc13.vhdl b/testsuite/gna/issue818/tc13.vhdl
new file mode 100644
index 000000000..c51dbed65
--- /dev/null
+++ b/testsuite/gna/issue818/tc13.vhdl
@@ -0,0 +1,17 @@
+entity tc13 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc13 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? tg and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc14.vhdl b/testsuite/gna/issue818/tc14.vhdl
new file mode 100644
index 000000000..f369cc6ca
--- /dev/null
+++ b/testsuite/gna/issue818/tc14.vhdl
@@ -0,0 +1,17 @@
+entity tc14 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc14 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if (?? tg) and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc15.vhdl b/testsuite/gna/issue818/tc15.vhdl
new file mode 100644
index 000000000..ca4131065
--- /dev/null
+++ b/testsuite/gna/issue818/tc15.vhdl
@@ -0,0 +1,17 @@
+entity tc15 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc15 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? (tg) and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc16.vhdl b/testsuite/gna/issue818/tc16.vhdl
new file mode 100644
index 000000000..25618e136
--- /dev/null
+++ b/testsuite/gna/issue818/tc16.vhdl
@@ -0,0 +1,17 @@
+entity tc16 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc16 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? tg and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc17.vhdl b/testsuite/gna/issue818/tc17.vhdl
new file mode 100644
index 000000000..be54331e4
--- /dev/null
+++ b/testsuite/gna/issue818/tc17.vhdl
@@ -0,0 +1,17 @@
+entity tc17 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc17 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if (?? tg) and falling_edge(clk) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc2.vhdl b/testsuite/gna/issue818/tc2.vhdl
new file mode 100644
index 000000000..f035e864c
--- /dev/null
+++ b/testsuite/gna/issue818/tc2.vhdl
@@ -0,0 +1,17 @@
+entity tc2 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc2 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc3.vhdl b/testsuite/gna/issue818/tc3.vhdl
new file mode 100644
index 000000000..9aebf41c4
--- /dev/null
+++ b/testsuite/gna/issue818/tc3.vhdl
@@ -0,0 +1,17 @@
+entity tc3 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc3 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if falling_edge(clk) and (tg) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc4.vhdl b/testsuite/gna/issue818/tc4.vhdl
new file mode 100644
index 000000000..037ad4105
--- /dev/null
+++ b/testsuite/gna/issue818/tc4.vhdl
@@ -0,0 +1,17 @@
+entity tc4 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc4 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if falling_edge(clk) and tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc5.vhdl b/testsuite/gna/issue818/tc5.vhdl
new file mode 100644
index 000000000..662224825
--- /dev/null
+++ b/testsuite/gna/issue818/tc5.vhdl
@@ -0,0 +1,17 @@
+entity tc5 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc5 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if falling_edge(clk) and ?? tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc6.vhdl b/testsuite/gna/issue818/tc6.vhdl
new file mode 100644
index 000000000..e998b0027
--- /dev/null
+++ b/testsuite/gna/issue818/tc6.vhdl
@@ -0,0 +1,17 @@
+entity tc6 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc6 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if falling_edge(clk) and (??tg) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc7.vhdl b/testsuite/gna/issue818/tc7.vhdl
new file mode 100644
index 000000000..204abbc4b
--- /dev/null
+++ b/testsuite/gna/issue818/tc7.vhdl
@@ -0,0 +1,17 @@
+entity tc7 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc7 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? falling_edge(clk) and (tg) then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc8.vhdl b/testsuite/gna/issue818/tc8.vhdl
new file mode 100644
index 000000000..77232b388
--- /dev/null
+++ b/testsuite/gna/issue818/tc8.vhdl
@@ -0,0 +1,17 @@
+entity tc8 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc8 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? falling_edge(clk) and tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/tc9.vhdl b/testsuite/gna/issue818/tc9.vhdl
new file mode 100644
index 000000000..c98b1359e
--- /dev/null
+++ b/testsuite/gna/issue818/tc9.vhdl
@@ -0,0 +1,17 @@
+entity tc9 is
+end;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tc9 is
+ signal clk : std_logic;
+ signal tg : std_logic;
+begin
+ process (clk) is
+ begin
+ if ?? falling_edge(clk) and ?? tg then
+ null;
+ end if;
+ end process;
+end behav;
diff --git a/testsuite/gna/issue818/testsuite.sh b/testsuite/gna/issue818/testsuite.sh
new file mode 100755
index 000000000..97db17966
--- /dev/null
+++ b/testsuite/gna/issue818/testsuite.sh
@@ -0,0 +1,39 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+
+analyze tc1.vhdl
+elab_simulate tc1
+
+analyze tc2.vhdl
+elab_simulate tc2
+
+analyze_failure tc3.vhdl
+analyze_failure tc4.vhdl
+analyze_failure tc5.vhdl
+
+analyze tc6.vhdl
+elab_simulate tc6
+
+analyze_failure tc7.vhdl
+analyze_failure tc8.vhdl
+analyze_failure tc9.vhdl
+analyze_failure tc10.vhdl
+analyze_failure tc11.vhdl
+analyze_failure tc12.vhdl
+analyze_failure tc13.vhdl
+
+analyze tc14.vhdl
+elab_simulate tc14
+
+analyze_failure tc15.vhdl
+analyze_failure tc16.vhdl
+
+analyze tc17.vhdl
+elab_simulate tc17
+
+clean
+
+echo "Test successful"
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-30 02:29:23 +0000