testsuite/gna/issue818/tc5.vhdl


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

entity tc5 is
end;

library ieee;
use ieee.std_logic_1164.all;

architecture behav of tc5 is
  signal clk : std_logic;
  signal tg : std_logic;
begin
  process (clk) is
  begin
    if falling_edge(clk) and ?? tg then
      null;
    end if;
  end process;
end behav;