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-rw-r--r--testsuite/gna/issue263/mac.vhdl77
-rw-r--r--testsuite/gna/issue263/mac_test.vhdl75
-rwxr-xr-xtestsuite/gna/issue263/testsuite.sh12
3 files changed, 164 insertions, 0 deletions
diff --git a/testsuite/gna/issue263/mac.vhdl b/testsuite/gna/issue263/mac.vhdl
new file mode 100644
index 000000000..ff05cb5cc
--- /dev/null
+++ b/testsuite/gna/issue263/mac.vhdl
@@ -0,0 +1,77 @@
+library ieee;
+use ieee.std_logic_1164.all, ieee.fixed_pkg.all;
+use ieee.math_complex.all;
+
+entity mac is
+ port( clk, reset : in std_ulogic;
+ x_real : in u_sfixed(0 downto -15);-- real and imaginary part of the two input data sequences
+ x_imag : in u_sfixed(0 downto -15);
+ y_real : in u_sfixed(0 downto -15);
+ y_imag : in u_sfixed(0 downto -15);
+ s_real : out u_sfixed(0 downto -15); --real and imaginary parts of accumulated sum
+ s_imag : out u_sfixed(0 downto -15);
+ ovf : out std_ulogic); --overflow flag
+end entity mac;
+
+
+-- Behavioral model of MAC algorithm allows for focus on the algorithm without being distracted
+-- by other details at this erly design stage.
+
+architecture behavioral of mac is
+ signal x_complex, y_complex, s_complex : complex;
+
+begin
+ x_complex <= ( to_real(x_real), to_real(x_imag) );
+ y_complex <= ( to_real(y_real), to_real(y_imag) );
+
+ behavior : process (clk) is
+ variable input_x, input_y : complex := (0.0, 0.0);
+ variable real_part_product_1, real_part_product_2,
+ imag_part_product_1, imag_part_product_2 : real := 0.0;
+ variable product, sum : complex := (0.0, 0.0);
+ variable real_accumulator_ovf,
+ imag_accumulator_ovf : boolean := false;
+ begin
+ if rising_edge(clk) then
+ -- Work from the end of the pipeline back to the start,
+ -- so as not to overwrite previosu results from the pipeline
+ -- registers before they are even used.
+
+ -- Update accumulator and generate outputs.
+ if reset then
+ sum := (0.0, 0.0);
+ real_accumulator_ovf := false;
+ imag_accumulator_ovf := false;
+ else
+ sum := product + sum;
+ real_accumulator_ovf := real_accumulator_ovf
+ or sum.re < -16.0
+ or sum.re >= +16.0;
+ imag_accumulator_ovf := imag_accumulator_ovf
+ or sum.im < -16.0
+ or sum.im >= +16.0;
+ end if;
+ s_complex <= sum;
+ ovf <= '1';
+ -- ovf <= '1' when (real_accumulator_ovf or imag_accumulator_ovf
+ -- or sum.re < -1.0 or sum.re >= +1.0
+ -- or sum.im < -1.0 or sum.im >= +1.0 ) else '0';
+ -- Update product registers
+ product.re := real_part_product_1 - real_part_product_2;
+ product.im := imag_part_product_1 + imag_part_product_2;
+
+ -- Update partial product registers
+ -- (actually with the full product).
+ real_part_product_1 := input_x.re * input_y.re;
+ real_part_product_2 := input_x.im * input_y.im;
+ imag_part_product_1 := input_x.re * input_y.re;
+ imag_part_product_2 := input_x.im * input_y.im;
+
+ -- Update input registers using MAC inputs
+ input_x := x_complex;
+ input_y := y_complex;
+ end if;
+ end process behavior;
+ s_real <= to_sfixed(s_complex.re, s_real);
+ s_imag <= to_sfixed(s_complex.im, s_imag);
+end architecture behavioral;
diff --git a/testsuite/gna/issue263/mac_test.vhdl b/testsuite/gna/issue263/mac_test.vhdl
new file mode 100644
index 000000000..6f8cb7e09
--- /dev/null
+++ b/testsuite/gna/issue263/mac_test.vhdl
@@ -0,0 +1,75 @@
+entity mac_test is
+end entity mac_test;
+
+library ieee;
+use ieee.std_logic_1164.all, ieee.fixed_pkg.all,
+ ieee.math_complex.all;
+
+architecture bench_behavioral of mac_test is
+
+ signal clk, reset, ovf : std_ulogic := '0';
+ signal x_real, x_imag,
+ y_real, y_imag,
+ s_real, s_imag : u_sfixed(0 downto -15);
+
+ signal x, y, s : complex := (0.0, 0.0);
+
+ constant Tpw_clk : time := 50 ns;
+
+begin
+
+ x_real <= x.re; x_imag <= x.im;
+ y_real <= y.re; y_imag <= y.im;
+
+ dut : entity work.mac(behavioral)
+ port map ( clk, reset,
+ x_real, x_imag, y_real, y_imag, s_real, s_imag,
+ ovf );
+
+ s <= (s_real, s_imag);
+
+ clock_gen : process is
+ begin
+ clk <= '1' after Tpw_clk, '0' after 2 * Tpw_clk;
+ wait for 2 * Tpw_clk;
+ end process clock_gen;
+
+ stimulus : process is
+ begin
+ -- first sequence
+ reset <= '1';
+ wait until not clk;
+ x <= (+0.5, +0.5); y <= (+0.5, +0.5); reset <= '1';
+ wait until not clk;
+ x <= (+0.2, +0.2); y <= (+0.2, +0.2); reset <= '1';
+ wait until not clk;
+ x <= (+0.1, -0.1); y <= (+0.1, +0.1); reset <= '1';
+ wait until not clk;
+ x <= (+0.1, -0.1); y <= (+0.1, +0.1); reset <= '0';
+ wait until not clk;
+
+ -- should be (0.04, 0.58) when it falls out the other end
+
+ reset <= '0';
+ wait until not clk;
+ x <= (+0.5, +0.5); y <= (+0.5, +0.5); reset <= '0';
+ wait until not clk;
+ x <= (+0.5, +0.5); y <= (+0.1, +0.1); reset <= '0';
+ wait until not clk;
+ x <= (+0.5, +0.5); y <= (+0.5, +0.5); reset <= '1';
+ wait until not clk;
+ x <= (-0.5, +0.5); y <= (-0.5, +0.5); reset <= '0';
+ wait until not clk;
+ reset <= '0';
+ wait until not clk;
+ reset <= '0';
+ wait until not clk;
+ reset <= '0';
+ wait until not clk;
+ reset <= '1';
+ wait until not clk;
+
+ wait;
+ end process stimulus;
+
+end architecture bench_behavioral;
diff --git a/testsuite/gna/issue263/testsuite.sh b/testsuite/gna/issue263/testsuite.sh
new file mode 100755
index 000000000..1cc2146fc
--- /dev/null
+++ b/testsuite/gna/issue263/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze mac.vhdl
+analyze_failure mac_test.vhdl
+#elab_simulate mac_test
+
+clean
+
+echo "Test successful"