diff options
Diffstat (limited to 'testsuite/pyunit/Current.vhdl')
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 30 |
1 files changed, 28 insertions, 2 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 8653cb088..ff03e1d04 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -20,16 +20,36 @@ end entity entity_1; architecture behav of entity_1 is constant MAX : positive := -25; - signal rst : std_logic := foo'('U'); + signal rst : std_logic := foo('U'); +-- signal vec : bit_vector(pack.input'bar'range); type newInt is range -4 to 3; + type newFp is range 4.3 downto -3.9; + type arr is array(natural range <>, enum range <>) of integer(3 downto 0); + type rec is record + elem1 : bit; + elem2 : boolean; + elem3 : integer_vector(3 downto 0); + elem4 : natural range 7 to 8; + end record; + type enum is (e1, e2, e3); + type acc is access bar; subtype uint8 is integer range 0 to 255; - function foo(a : integer; b : boolean) return bit is +-- file f : text; + + function func (a : integer; b : boolean) return bit is begin end function; + shared variable pt_var : lib.pack.prot; + + procedure proc(spam : egg) is + begin + + end procedure; + alias bar is boolean; begin process(Clock) @@ -46,6 +66,12 @@ end architecture behav; package package_1 is constant ghdl : float := (3, 5, 0 to 2 => 5, 3 => 4, name => 10); -- 2.3; + + component comp is + port ( + clk : std + ); + end component; end package; package body package_1 is |