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Diffstat (limited to 'testsuite/pyunit/lsp/files/adder.vhdl')
| -rw-r--r-- | testsuite/pyunit/lsp/files/adder.vhdl | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/testsuite/pyunit/lsp/files/adder.vhdl b/testsuite/pyunit/lsp/files/adder.vhdl new file mode 100644 index 000000000..38ff2a60f --- /dev/null +++ b/testsuite/pyunit/lsp/files/adder.vhdl @@ -0,0 +1,16 @@ + +entity adder is + -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder. + -- `s` is the sum output, `co` is the carry-out. + port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); +end adder; + +architecture rtl of adder is +begin + -- This full-adder architecture contains two concurrent assignments. + -- Compute the sum. + s <= i0 xor i1 xor ci; + -- Compute the carry. + co <= (i0 and i1) or (i0 and ci) or (i1 and ci); +end rtl; + |