4 files changed, 78 insertions, 16 deletions
diff --git a/testsuite/pyunit/SimplePackage.vhdl b/testsuite/pyunit/SimplePackage.vhdl
deleted file mode 100644
index dca7e15dc..000000000
--- a/testsuite/pyunit/SimplePackage.vhdl
+++ /dev/null
@@ -1,15 +0,0 @@
-library ieee;
-use     ieee.std_logic_1164.all;
-use     ieee.numeric_std.all;
-
--- Documentation before pack_1
-package pack_1 is
-	-- Global constant const_1
-	constant const_1 : boolean := false;
-
-end package;
-
-package body pack_1 is
-	constant const_2 : boolean := true;
-
-end package body;
diff --git a/testsuite/pyunit/dom/SimpleEntity.py b/testsuite/pyunit/dom/Simple.py
index c2167c973..32033609d 100644
--- a/testsuite/pyunit/dom/SimpleEntity.py
+++ b/testsuite/pyunit/dom/Simple.py
@@ -44,7 +44,7 @@ if __name__ == "__main__":
 
 class SimpleEntity(TestCase):
     _root = Path(__file__).resolve().parent.parent
-    _filename: Path = _root / "SimpleEntity.vhdl"
+    _filename: Path = _root / "dom/examples/SimpleEntity.vhdl"
 
     def test_Design(self):
         design = Design()
@@ -89,3 +89,52 @@ class SimpleEntity(TestCase):
         print()
         print(architecture.Documentation)
         self.assertEqual(1, len(architecture.Documentation.splitlines()))
+
+
+class SimplePackage(TestCase):
+    _root = Path(__file__).resolve().parent.parent
+    _filename: Path = _root / "dom/examples/SimplePackage.vhdl"
+
+    def test_Design(self):
+        design = Design()
+
+        self.assertIsNotNone(design)
+
+    # def test_Library(self):
+    # 	library = Library()
+
+    def test_Document(self):
+        design = Design()
+        document = Document(self._filename)
+        design.Documents.append(document)
+
+        self.assertEqual(1, len(design.Documents))
+        print()
+        print(document.Documentation)
+        self.assertEqual(4, len(document.Documentation.splitlines()))
+
+    def test_Package(self):
+        design = Design()
+        document = Document(self._filename)
+        design.Documents.append(document)
+
+        self.assertEqual(1, len(design.Documents[0].Packages))
+
+        package = design.Documents[0].Packages[0]
+        self.assertEqual("utilities", package.Identifier)
+        print()
+        print(package.Documentation)
+        self.assertEqual(1, len(package.Documentation.splitlines()))
+
+    def test_PackageBody(self):
+        design = Design()
+        document = Document(self._filename)
+        design.Documents.append(document)
+
+        self.assertEqual(1, len(design.Documents[0].PackageBodies))
+
+        packageBodies = design.Documents[0].PackageBodies[0]
+        self.assertEqual("utilities", packageBodies.Identifier)
+        print()
+        print(packageBodies.Documentation)
+        self.assertEqual(0, len(packageBodies.Documentation.splitlines()))
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl
index bdeae47e1..bdeae47e1 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl
diff --git a/testsuite/pyunit/dom/examples/SimplePackage.vhdl b/testsuite/pyunit/dom/examples/SimplePackage.vhdl
new file mode 100644
index 000000000..04df1c521
--- /dev/null
+++ b/testsuite/pyunit/dom/examples/SimplePackage.vhdl
@@ -0,0 +1,28 @@
+-- Author: Patrick Lehmann
+--
+-- A collection of utility types and functions.
+--
+library ieee;
+use     ieee.std_logic_1164.all;
+use     ieee.numeric_std.all;
+
+-- Utility package
+package utilities is
+	-- Deferred constant to distinguish simulation from synthesis.
+	constant IS_SIMULATION : boolean;
+
+end package;
+
+package body utilities is
+	function simulation return boolean is
+		variable result : boolean := false;
+	begin
+		-- synthesis translate off
+		result := true;
+		-- synthesis translate on
+		return result;
+	end function;
+
+	constant IS_SIMULATION : boolean := simulation;
+
+end package body;