1 files changed, 7 insertions, 7 deletions
diff --git a/testsuite/synth/issue1090/simple_ram.vhdl b/testsuite/synth/issue1090/simple_ram.vhdl
index 345083850..99187a681 100644
--- a/testsuite/synth/issue1090/simple_ram.vhdl
+++ b/testsuite/synth/issue1090/simple_ram.vhdl
@@ -35,11 +35,11 @@ entity simple_ram is
 
     en : in std_logic;
     raddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
-    do : out std_logic_vector(31 downto 0);
+    dout : out std_logic_vector(31 downto 0);
 
     we : in std_logic_vector(3 downto 0);
     waddr : in std_logic_vector(ADDR_WIDTH - 3 downto 0);
-    di : in std_logic_vector(31 downto 0)
+    din : in std_logic_vector(31 downto 0)
     );
 end simple_ram;
 
@@ -55,19 +55,19 @@ begin
   begin
     if clk'event and clk = '1' and en = '1' then -- Unsupported: clock enable
       if we(3) = '1' then
-        ram(to_integer(unsigned(waddr)))(31 downto 24) <= di(31 downto 24);
+        ram(to_integer(unsigned(waddr)))(31 downto 24) <= din(31 downto 24);
       end if;
       if we(2) = '1' then
-        ram(to_integer(unsigned(waddr)))(23 downto 16) <= di(23 downto 16);
+        ram(to_integer(unsigned(waddr)))(23 downto 16) <= din(23 downto 16);
       end if;
       if we(1) = '1' then
-        ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= di(15 downto 8 );
+        ram(to_integer(unsigned(waddr)))(15 downto 8 ) <= din(15 downto 8 );
       end if;
       if we(0) = '1' then
-        ram(to_integer(unsigned(waddr)))(7  downto 0 ) <= di(7  downto 0 );
+        ram(to_integer(unsigned(waddr)))(7  downto 0 ) <= din(7  downto 0 );
       end if;
       read := ram(to_integer(unsigned(raddr)));
-      do <= read;
+      dout <= read;
     end if;
   end process;
 end behavioral;