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-rw-r--r--testsuite/synth/issue1273/assert4.vhdl21
1 files changed, 21 insertions, 0 deletions
diff --git a/testsuite/synth/issue1273/assert4.vhdl b/testsuite/synth/issue1273/assert4.vhdl
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+++ b/testsuite/synth/issue1273/assert4.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert4 is
+ port (v : std_logic_Vector (7 downto 0);
+ en : std_logic;
+ clk : std_logic;
+ res : out std_logic);
+end;
+
+architecture behav of assert4 is
+begin
+ process (clk)
+ begin
+ if rising_edge(clk) and en = '1' then
+ assert v /= x"00";
+ res <= v(0) xor v(1);
+ end if;
+ end process;
+end behav;
+