1 files changed, 20 insertions, 0 deletions
diff --git a/testsuite/synth/issue1591/repro2.vhdl b/testsuite/synth/issue1591/repro2.vhdl
new file mode 100644
index 000000000..c0ef4f21a
--- /dev/null
+++ b/testsuite/synth/issue1591/repro2.vhdl
@@ -0,0 +1,20 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+
+entity repro1 is
+  port (clk : in std_logic);
+end entity repro1;
+
+architecture psl of repro1 is
+begin
+  testG : if true generate
+    signal b : boolean := true;
+  begin
+    -- All is sensitive to rising edge of clk
+    default clock is rising_edge(clk);
+
+    -- This assertion generates an ghdl-yosys-plugin error
+    -- ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
+    INITIAL_1_a : assert always b;
+  end generate testG;
+end architecture psl;