1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue1609/exp_vhd.vhdl b/testsuite/synth/issue1609/exp_vhd.vhdl
new file mode 100644
index 000000000..06a6260d7
--- /dev/null
+++ b/testsuite/synth/issue1609/exp_vhd.vhdl
@@ -0,0 +1,26 @@
+library IEEE;
+  use IEEE.std_logic_1164.ALL;
+  use IEEE.numeric_std.ALL;
+
+entity exp is
+  port (
+    clk : in    std_logic
+  );
+end entity exp;
+
+architecture behav of exp is
+
+  signal any_nat : natural;
+
+  attribute anyconst : boolean;
+  attribute anyconst of any_nat : signal is true;
+
+begin
+
+  default Clock is rising_edge(clk);
+
+  assume always any_nat >=10;
+  assert always any_nat >=10;
+
+end architecture behav;
+