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-rw-r--r--testsuite/synth/issue2279/ent.vhdl18
1 files changed, 18 insertions, 0 deletions
diff --git a/testsuite/synth/issue2279/ent.vhdl b/testsuite/synth/issue2279/ent.vhdl
new file mode 100644
index 000000000..6c33c60d3
--- /dev/null
+++ b/testsuite/synth/issue2279/ent.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+ generic(
+ DATA_WIDTH : integer := 8
+ );
+end;
+
+architecture arch of ent is
+ signal a : std_logic_vector(DATA_WIDTH-1 downto 0);
+ signal b : std_logic;
+ signal c : std_logic_vector(DATA_WIDTH+1-1 downto 0);
+begin
+ (a, b) <= c;
+end;
+