diff options
Diffstat (limited to 'testsuite/synth/issue662/psl_onehot0.vhdl')
-rw-r--r-- | testsuite/synth/issue662/psl_onehot0.vhdl | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/psl_onehot0.vhdl b/testsuite/synth/issue662/psl_onehot0.vhdl new file mode 100644 index 000000000..edd4361c8 --- /dev/null +++ b/testsuite/synth/issue662/psl_onehot0.vhdl @@ -0,0 +1,27 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity psl_onehot0 is + port (clk : in std_logic; + a, b : in std_logic_vector(3 downto 0); + c : in natural range 0 to 15 + ); +end entity psl_onehot0; + + +architecture psl of psl_onehot0 is +begin + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion holds + ONEHOT0_0_a : assert always onehot0(a); + + -- This assertion fails at cycle 15 + ONEHOT0_1_a : assert always onehot0(b); + + -- This assertion fails at cycle 15 + ONEHOT0_2_a : assert always onehot(c); + +end architecture psl; |