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-rw-r--r--testsuite/synth/issue662/tb_psl_onehot.vhdl5
1 files changed, 1 insertions, 4 deletions
diff --git a/testsuite/synth/issue662/tb_psl_onehot.vhdl b/testsuite/synth/issue662/tb_psl_onehot.vhdl
index 10b5d8c73..0bf60bf5d 100644
--- a/testsuite/synth/issue662/tb_psl_onehot.vhdl
+++ b/testsuite/synth/issue662/tb_psl_onehot.vhdl
@@ -51,12 +51,11 @@ architecture psl of tb_psl_onehot is
end hseq;
signal a, b : std_logic_vector(3 downto 0) := x"0";
- signal c : natural range 0 to 15 := 0;
signal clk : std_logic := '1';
begin
- dut: entity work.psl_onehot port map (clk, a, b, c);
+ dut: entity work.psl_onehot port map (clk, a, b);
clk <= not clk after 500 ps;
@@ -64,6 +63,4 @@ begin
SEQ_A : hseq ("111222444888888", clk, a);
SEQ_B : hseq ("111222444888999", clk, b);
- c <= to_integer(unsigned(b));
-
end architecture psl;