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-rw-r--r--testsuite/synth/synth50/slv_negation.vhdl14
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/synth50/slv_negation.vhdl b/testsuite/synth/synth50/slv_negation.vhdl
new file mode 100644
index 000000000..5161f9639
--- /dev/null
+++ b/testsuite/synth/synth50/slv_negation.vhdl
@@ -0,0 +1,14 @@
+library ieee;
+ use ieee.std_logic_1164.all;
+
+entity slv_negation is
+ port (
+ a : in std_logic_vector(7 downto 0);
+ b : out std_logic_vector(7 downto 0)
+ );
+end slv_negation;
+
+architecture rtl of slv_negation is
+begin
+ b <= not a(7 downto 0);
+end rtl;