5 files changed, 92 insertions, 0 deletions
diff --git a/testsuite/synth/issue1421/repro.vhdl b/testsuite/synth/issue1421/repro.vhdl
new file mode 100644
index 000000000..4b8b435b5
--- /dev/null
+++ b/testsuite/synth/issue1421/repro.vhdl
@@ -0,0 +1,21 @@
+entity repro is
+  port (clk : bit;
+        rst : bit;
+        v : bit_vector (3 downto 0);
+        res : out bit_vector(3 downto 0));
+end;
+
+architecture behav of repro is
+begin
+  process (clk)
+  begin
+    if clk'event and clk = '1' then
+      res <= v;
+      if rst = '1' then
+        res <= "0000";
+      end if;
+    end if;
+    res (2) <= '0';
+  end process;
+end behav;
+      
diff --git a/testsuite/synth/issue1421/repro2.vhdl b/testsuite/synth/issue1421/repro2.vhdl
new file mode 100644
index 000000000..6feec8576
--- /dev/null
+++ b/testsuite/synth/issue1421/repro2.vhdl
@@ -0,0 +1,28 @@
+entity repro2 is
+  port (clk : bit;
+        rst : bit;
+        v : bit_vector (1 downto 0);
+        res : out bit_vector(1 downto 0));
+end;
+
+architecture behav of repro2 is
+  type myrec is record
+    b : bit;
+    c : bit;
+  end record;
+  signal s, sin : myrec;
+begin
+  sin <= (v(1), v(0));
+
+  process (clk)
+  begin
+    if clk'event and clk = '1' then
+      s <= sin;
+    end if;
+    if rst = '0' then
+      s.c <= '0';
+    end if;
+  end process;
+
+  res <= (s.c, s.b);
+end behav;
diff --git a/testsuite/synth/issue1421/repro3.vhdl b/testsuite/synth/issue1421/repro3.vhdl
new file mode 100644
index 000000000..4fa0f4738
--- /dev/null
+++ b/testsuite/synth/issue1421/repro3.vhdl
@@ -0,0 +1,16 @@
+entity repro3 is
+  port (clk : bit;
+        v : bit_vector (1 downto 0);
+        res : out bit_vector(1 downto 0));
+end;
+
+architecture behav of repro3 is
+begin
+  process (clk)
+  begin
+    if clk'event and clk = '1' then
+      res <= v;
+    end if;
+    res (0) <= '0';
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1421/repro4.vhdl b/testsuite/synth/issue1421/repro4.vhdl
new file mode 100644
index 000000000..4fa0f4738
--- /dev/null
+++ b/testsuite/synth/issue1421/repro4.vhdl
@@ -0,0 +1,16 @@
+entity repro3 is
+  port (clk : bit;
+        v : bit_vector (1 downto 0);
+        res : out bit_vector(1 downto 0));
+end;
+
+architecture behav of repro3 is
+begin
+  process (clk)
+  begin
+    if clk'event and clk = '1' then
+      res <= v;
+    end if;
+    res (0) <= '0';
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1421/testsuite.sh b/testsuite/synth/issue1421/testsuite.sh
new file mode 100755
index 000000000..fe9cc3835
--- /dev/null
+++ b/testsuite/synth/issue1421/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_analyze repro3
+
+# Look for a dff.
+grep -q "if rising_edge (wrap_clk) then" syn_repro3.vhdl
+clean
+
+echo "Test successful"