3 files changed, 74 insertions, 0 deletions
diff --git a/testsuite/synth/stmt01/forloop2.vhdl b/testsuite/synth/stmt01/forloop2.vhdl
new file mode 100644
index 000000000..67ed6b485
--- /dev/null
+++ b/testsuite/synth/stmt01/forloop2.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity forloop2 is
+  port (vin: in STD_LOGIC_VECTOR (7 downto 0);
+        vout: out STD_LOGIC_VECTOR (3 downto 0);
+        clk: in STD_LOGIC);
+end forloop2;
+
+architecture behav of forloop2 is
+begin
+  process (clk, vin)
+    variable count: unsigned (vout'range);
+  begin
+    if rising_edge (clk)
+    then
+      count := (others => '0');
+      for I in vin'range loop
+        count := count + unsigned'(0 => vin (i));
+      end loop;
+      vout <= std_logic_vector (count);
+    end if;
+  end process;
+end behav;
+
diff --git a/testsuite/synth/stmt01/tb_forloop2.vhdl b/testsuite/synth/stmt01/tb_forloop2.vhdl
new file mode 100644
index 000000000..9ae956da6
--- /dev/null
+++ b/testsuite/synth/stmt01/tb_forloop2.vhdl
@@ -0,0 +1,32 @@
+entity tb_forloop2 is
+end tb_forloop2;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_forloop2 is
+  signal vin : std_logic_vector (7 downto 0);
+  signal vout : std_logic_vector (3 downto 0);
+  signal clk : std_logic;
+  signal b : std_logic;
+  signal c : std_logic;
+  signal z : std_logic;
+begin
+  dut: entity work.forloop2
+    port map (vin => vin, vout => vout, clk => clk);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 1 ns;
+      clk <= '1';
+      wait for 1 ns;
+    end pulse;
+  begin
+    vin <= x"00";
+    pulse;
+    assert vout = x"0" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/stmt01/testsuite.sh b/testsuite/synth/stmt01/testsuite.sh
new file mode 100755
index 000000000..3d066e799
--- /dev/null
+++ b/testsuite/synth/stmt01/testsuite.sh
@@ -0,0 +1,16 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in forloop2; do
+    analyze $t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+
+    synth $t.vhdl -e $t > syn_$t.vhdl
+    analyze syn_$t.vhdl tb_$t.vhdl
+    elab_simulate tb_$t
+    clean
+done
+
+echo "Test successful"