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-rw-r--r--testsuite/synth/issue1069/ram4.vhdl8
-rw-r--r--testsuite/synth/issue1069/ram41.vhdl6
-rw-r--r--testsuite/synth/issue1069/ram5.vhdl8
-rw-r--r--testsuite/synth/issue1069/tb_ram3.vhdl90
-rw-r--r--testsuite/synth/issue1069/tb_ram4.vhdl88
-rw-r--r--testsuite/synth/issue1069/tb_ram41.vhdl88
-rw-r--r--testsuite/synth/issue1069/tb_ram5.vhdl88
-rwxr-xr-xtestsuite/synth/issue1069/testsuite.sh3
8 files changed, 368 insertions, 11 deletions
diff --git a/testsuite/synth/issue1069/ram4.vhdl b/testsuite/synth/issue1069/ram4.vhdl
index 3321e59c1..41792e8b3 100644
--- a/testsuite/synth/issue1069/ram4.vhdl
+++ b/testsuite/synth/issue1069/ram4.vhdl
@@ -2,9 +2,9 @@ library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
-entity tdp_ram is
+entity ram4 is
generic (
- ADDRWIDTH : positive := 7;
+ ADDRWIDTH : positive := 12;
WIDTH : positive := 8
);
port (
@@ -22,9 +22,9 @@ entity tdp_ram is
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
-end tdp_ram;
+end ram4;
-architecture behavioral of tdp_ram is
+architecture behavioral of ram4 is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
diff --git a/testsuite/synth/issue1069/ram41.vhdl b/testsuite/synth/issue1069/ram41.vhdl
index 7e5b2e296..fe8afbaa2 100644
--- a/testsuite/synth/issue1069/ram41.vhdl
+++ b/testsuite/synth/issue1069/ram41.vhdl
@@ -2,7 +2,7 @@ library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
-entity tdp_ram is
+entity ram41 is
generic (
ADDRWIDTH : positive := 7;
WIDTH : positive := 8
@@ -22,9 +22,9 @@ entity tdp_ram is
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
-end tdp_ram;
+end ram41;
-architecture behavioral of tdp_ram is
+architecture behavioral of ram41 is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
diff --git a/testsuite/synth/issue1069/ram5.vhdl b/testsuite/synth/issue1069/ram5.vhdl
index 4fed38abf..f846137dc 100644
--- a/testsuite/synth/issue1069/ram5.vhdl
+++ b/testsuite/synth/issue1069/ram5.vhdl
@@ -2,9 +2,9 @@ library ieee;
use ieee.std_logic_1164.all,
ieee.numeric_std.all;
-entity tdp_ram is
+entity ram5 is
generic (
- ADDRWIDTH : positive := 7;
+ ADDRWIDTH : positive := 12;
WIDTH : positive := 8
);
port (
@@ -22,9 +22,9 @@ entity tdp_ram is
data_read_b : out std_logic_vector(WIDTH - 1 downto 0);
data_write_b : in std_logic_vector(WIDTH - 1 downto 0)
);
-end tdp_ram;
+end ram5;
-architecture behavioral of tdp_ram is
+architecture behavioral of ram5 is
begin
process(clk_a, clk_b)
type ram_t is array(0 to 2**ADDRWIDTH - 1) of std_logic_vector(WIDTH - 1 downto 0);
diff --git a/testsuite/synth/issue1069/tb_ram3.vhdl b/testsuite/synth/issue1069/tb_ram3.vhdl
new file mode 100644
index 000000000..8b56df37f
--- /dev/null
+++ b/testsuite/synth/issue1069/tb_ram3.vhdl
@@ -0,0 +1,90 @@
+entity tb_ram3 is
+end tb_ram3;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram3 is
+ constant WIDTH : natural := 8;
+ constant ADDRWIDTH : natural := 12;
+
+ signal clk_a : std_logic;
+ signal read_a : std_logic;
+ signal write_a : std_logic;
+ signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal clk_b : std_logic;
+ signal read_b : std_logic;
+ signal write_b : std_logic;
+ signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_b : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_b : std_logic_vector(WIDTH - 1 downto 0);
+begin
+ tdp_ram_1: entity work.ram3
+ generic map (
+ ADDRWIDTH => ADDRWIDTH,
+ WIDTH => WIDTH)
+ port map (
+ clk_a => clk_a,
+ read_a => read_a,
+ write_a => write_a,
+ addr_a => addr_a,
+ data_read_a => data_read_a,
+ data_write_a => data_write_a,
+ clk_b => clk_b,
+ read_b => read_b,
+ write_b => write_b,
+ addr_b => addr_b,
+ data_read_b => data_read_b,
+ data_write_b => data_write_b);
+
+ process
+ procedure pulsea is
+ begin
+ clk_a <= '0';
+ wait for 1 ns;
+ clk_a <= '1';
+ wait for 1 ns;
+ end pulsea;
+
+ procedure pulseb is
+ begin
+ clk_b <= '0';
+ wait for 1 ns;
+ clk_b <= '1';
+ wait for 1 ns;
+ end pulseb;
+ begin
+ clk_a <= '0';
+ clk_b <= '0';
+
+ write_a <= '1';
+ read_a <= '0';
+ addr_a <= x"000";
+ data_write_a <= x"a0";
+ pulsea;
+
+ write_b <= '1';
+ read_b <= '0';
+ addr_b <= x"001";
+ data_write_b <= x"b1";
+ pulseb;
+
+ write_a <= '0';
+ read_a <= '1';
+ addr_a <= x"001";
+ pulsea;
+ pulsea;
+ assert data_read_a = x"b1" severity failure;
+
+ write_b <= '0';
+ read_b <= '1';
+ addr_b <= x"000";
+ pulseb;
+ pulseb;
+ assert data_read_b = x"a0" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1069/tb_ram4.vhdl b/testsuite/synth/issue1069/tb_ram4.vhdl
new file mode 100644
index 000000000..a33c0db5c
--- /dev/null
+++ b/testsuite/synth/issue1069/tb_ram4.vhdl
@@ -0,0 +1,88 @@
+entity tb_ram4 is
+end tb_ram4;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram4 is
+ constant WIDTH : natural := 8;
+ constant ADDRWIDTH : natural := 12;
+
+ signal clk_a : std_logic;
+ signal read_a : std_logic;
+ signal write_a : std_logic;
+ signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal clk_b : std_logic;
+ signal read_b : std_logic;
+ signal write_b : std_logic;
+ signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_b : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_b : std_logic_vector(WIDTH - 1 downto 0);
+begin
+ tdp_ram_1: entity work.ram4
+ generic map (
+ ADDRWIDTH => ADDRWIDTH,
+ WIDTH => WIDTH)
+ port map (
+ clk_a => clk_a,
+ read_a => read_a,
+ write_a => write_a,
+ addr_a => addr_a,
+ data_read_a => data_read_a,
+ data_write_a => data_write_a,
+ clk_b => clk_b,
+ read_b => read_b,
+ write_b => write_b,
+ addr_b => addr_b,
+ data_read_b => data_read_b,
+ data_write_b => data_write_b);
+
+ process
+ procedure pulsea is
+ begin
+ clk_a <= '0';
+ wait for 1 ns;
+ clk_a <= '1';
+ wait for 1 ns;
+ end pulsea;
+
+ procedure pulseb is
+ begin
+ clk_b <= '0';
+ wait for 1 ns;
+ clk_b <= '1';
+ wait for 1 ns;
+ end pulseb;
+ begin
+ clk_a <= '0';
+ clk_b <= '0';
+
+ write_a <= '1';
+ read_a <= '0';
+ addr_a <= x"000";
+ data_write_a <= x"a0";
+ pulsea;
+
+ write_b <= '1';
+ read_b <= '0';
+ addr_b <= x"001";
+ data_write_b <= x"b1";
+ pulseb;
+
+ write_a <= '0';
+ read_a <= '1';
+ addr_a <= x"001";
+ pulsea;
+ assert data_read_a = x"b1" severity failure;
+
+ write_b <= '0';
+ read_b <= '1';
+ addr_b <= x"000";
+ pulseb;
+ assert data_read_b = x"a0" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1069/tb_ram41.vhdl b/testsuite/synth/issue1069/tb_ram41.vhdl
new file mode 100644
index 000000000..dded6b21a
--- /dev/null
+++ b/testsuite/synth/issue1069/tb_ram41.vhdl
@@ -0,0 +1,88 @@
+entity tb_ram41 is
+end tb_ram41;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram41 is
+ constant WIDTH : natural := 8;
+ constant ADDRWIDTH : natural := 12;
+
+ signal clk_a : std_logic;
+ signal read_a : std_logic;
+ signal write_a : std_logic;
+ signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal clk_b : std_logic;
+ signal read_b : std_logic;
+ signal write_b : std_logic;
+ signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_b : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_b : std_logic_vector(WIDTH - 1 downto 0);
+begin
+ tdp_ram_1: entity work.ram41
+ generic map (
+ ADDRWIDTH => ADDRWIDTH,
+ WIDTH => WIDTH)
+ port map (
+ clk_a => clk_a,
+ read_a => read_a,
+ write_a => write_a,
+ addr_a => addr_a,
+ data_read_a => data_read_a,
+ data_write_a => data_write_a,
+ clk_b => clk_b,
+ read_b => read_b,
+ write_b => write_b,
+ addr_b => addr_b,
+ data_read_b => data_read_b,
+ data_write_b => data_write_b);
+
+ process
+ procedure pulsea is
+ begin
+ clk_a <= '0';
+ wait for 1 ns;
+ clk_a <= '1';
+ wait for 1 ns;
+ end pulsea;
+
+ procedure pulseb is
+ begin
+ clk_b <= '0';
+ wait for 1 ns;
+ clk_b <= '1';
+ wait for 1 ns;
+ end pulseb;
+ begin
+ clk_a <= '0';
+ clk_b <= '0';
+
+ write_a <= '1';
+ read_a <= '0';
+ addr_a <= x"000";
+ data_write_a <= x"a0";
+ pulsea;
+
+ write_b <= '1';
+ read_b <= '0';
+ addr_b <= x"001";
+ data_write_b <= x"b1";
+ pulseb;
+
+ write_a <= '0';
+ read_a <= '1';
+ addr_a <= x"001";
+ pulsea;
+ assert data_read_a = x"b1" severity failure;
+
+ write_b <= '0';
+ read_b <= '1';
+ addr_b <= x"000";
+ pulseb;
+ assert data_read_b = x"a0" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1069/tb_ram5.vhdl b/testsuite/synth/issue1069/tb_ram5.vhdl
new file mode 100644
index 000000000..828d64913
--- /dev/null
+++ b/testsuite/synth/issue1069/tb_ram5.vhdl
@@ -0,0 +1,88 @@
+entity tb_ram5 is
+end tb_ram5;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ram5 is
+ constant WIDTH : natural := 8;
+ constant ADDRWIDTH : natural := 12;
+
+ signal clk_a : std_logic;
+ signal read_a : std_logic;
+ signal write_a : std_logic;
+ signal addr_a : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_a : std_logic_vector(WIDTH - 1 downto 0);
+ signal clk_b : std_logic;
+ signal read_b : std_logic;
+ signal write_b : std_logic;
+ signal addr_b : std_logic_vector(ADDRWIDTH - 1 downto 0);
+ signal data_read_b : std_logic_vector(WIDTH - 1 downto 0);
+ signal data_write_b : std_logic_vector(WIDTH - 1 downto 0);
+begin
+ tdp_ram_1: entity work.ram5
+ generic map (
+ ADDRWIDTH => ADDRWIDTH,
+ WIDTH => WIDTH)
+ port map (
+ clk_a => clk_a,
+ read_a => read_a,
+ write_a => write_a,
+ addr_a => addr_a,
+ data_read_a => data_read_a,
+ data_write_a => data_write_a,
+ clk_b => clk_b,
+ read_b => read_b,
+ write_b => write_b,
+ addr_b => addr_b,
+ data_read_b => data_read_b,
+ data_write_b => data_write_b);
+
+ process
+ procedure pulsea is
+ begin
+ clk_a <= '0';
+ wait for 1 ns;
+ clk_a <= '1';
+ wait for 1 ns;
+ end pulsea;
+
+ procedure pulseb is
+ begin
+ clk_b <= '0';
+ wait for 1 ns;
+ clk_b <= '1';
+ wait for 1 ns;
+ end pulseb;
+ begin
+ clk_a <= '0';
+ clk_b <= '0';
+
+ write_a <= '1';
+ read_a <= '0';
+ addr_a <= x"000";
+ data_write_a <= x"a0";
+ pulsea;
+
+ write_b <= '1';
+ read_b <= '0';
+ addr_b <= x"001";
+ data_write_b <= x"b1";
+ pulseb;
+
+ write_a <= '0';
+ read_a <= '1';
+ addr_a <= x"001";
+ pulsea;
+ assert data_read_a = x"b1" severity failure;
+
+ write_b <= '0';
+ read_b <= '1';
+ addr_b <= x"000";
+ pulseb;
+ assert data_read_b = x"a0" severity failure;
+
+ wait;
+ end process;
+end behav;
diff --git a/testsuite/synth/issue1069/testsuite.sh b/testsuite/synth/issue1069/testsuite.sh
index 49a8e2905..e4e2da238 100755
--- a/testsuite/synth/issue1069/testsuite.sh
+++ b/testsuite/synth/issue1069/testsuite.sh
@@ -4,6 +4,9 @@
synth_analyze tdp_ram
synth_tb ram3
+synth_tb ram4
+#synth_tb ram41
+synth_tb ram5
clean
echo "Test successful"
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 04:19:53 +0000