2 files changed, 62 insertions, 0 deletions
diff --git a/testsuite/synth/var01/tb_var06.vhdl b/testsuite/synth/var01/tb_var06.vhdl
new file mode 100644
index 000000000..492bcefb4
--- /dev/null
+++ b/testsuite/synth/var01/tb_var06.vhdl
@@ -0,0 +1,38 @@
+entity tb_var06 is
+end tb_var06;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_var06 is
+  signal clk : std_logic;
+  signal mask : std_logic_vector (1 downto 0);
+  signal val : std_logic_vector (15 downto 0);
+  signal res : std_logic_vector (15 downto 0);
+begin
+  dut: entity work.var06
+    port map (
+      mask => mask,
+      val => val,
+      res => res);
+
+  process
+  begin
+    mask <= "11";
+    val <= x"aa_bb";
+    wait for 1 ns;
+    assert res = x"aa_bb" severity failure;
+
+    mask <= "00";
+    val <= x"12_34";
+    wait for 1 ns;
+    assert res = x"00_00" severity failure;
+
+    mask <= "10";
+    val <= x"12_34";
+    wait for 1 ns;
+    assert res = x"12_00" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/var01/var06.vhdl b/testsuite/synth/var01/var06.vhdl
new file mode 100644
index 000000000..ca7f103b2
--- /dev/null
+++ b/testsuite/synth/var01/var06.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity var06 is
+  port (mask : std_logic_vector (1 downto 0);
+        val : std_logic_vector (15 downto 0);
+        res : out std_logic_vector (15 downto 0));
+end var06;
+
+architecture behav of var06 is
+begin
+  process (all)
+    variable t : std_logic_vector (15 downto 0);
+  begin
+    t := (others => '0');
+    if mask (0) = '1' then
+      t (7 downto 0) := val (7 downto 0);
+    end if;
+    if mask (1) = '1' then
+      t (15 downto 8) := val (15 downto 8);
+    end if;
+    res <= t;
+  end process;
+end behav;