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Diffstat (limited to 'testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd')
-rw-r--r-- | testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd | 69 |
1 files changed, 69 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd new file mode 100644 index 000000000..8e4ecdc2a --- /dev/null +++ b/testsuite/vests/vhdl-93/ashenden/compliant/ch_05_tb_05_07.vhd @@ -0,0 +1,69 @@ + +-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: ch_05_tb_05_07.vhd,v 1.1.1.1 2001-08-22 18:20:48 paw Exp $ +-- $Revision: 1.1.1.1 $ +-- +-- --------------------------------------------------------------------- + +architecture functional of S_R_flipflop is + +begin + + q <= '1' when s = '1' else + '0' when r = '1'; + + q_n <= '0' when s = '1' else + '1' when r = '1'; + +end architecture functional; + + +entity tb_05_07 is +end entity tb_05_07; + + +architecture test of tb_05_07 is + + signal s, r : bit := '0'; + signal q, q_n : bit; + +begin + + dut : entity work.S_R_flipflop(functional) + port map ( s => s, r => r, q => q, q_n => q_n ); + + stimulus : process is + begin + wait for 10 ns; + s <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '1'; wait for 10 ns; + r <= '0'; wait for 10 ns; + s <= '1'; wait for 10 ns; + r <= '1'; wait for 10 ns; + s <= '0'; wait for 10 ns; + r <= '0'; wait for 10 ns; + + wait; + end process stimulus; + +end architecture test; |