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-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl35
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl23
-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl13
3 files changed, 71 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
new file mode 100644
index 000000000..1e479aa8f
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/integer-fanout.vhdl
@@ -0,0 +1,35 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ assign: process
+ begin -- process p
+ sig <= 1;
+ wait;
+ end process assign;
+
+ check1: process
+ begin -- process check1
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ wait;
+ end process check1;
+
+ check2: process
+ begin -- process check1
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ wait;
+ end process check2;
+
+ check3: process
+ begin -- process check1
+ wait for 2 fs;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process check3;
+
+
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
new file mode 100644
index 000000000..3efa37b6e
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-assign.vhdl
@@ -0,0 +1,23 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ p: process
+ begin -- process p
+ sig <= 1;
+ wait for 1 fs;
+ assert sig = 1 report "TEST FAILED" severity FAILURE;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process p;
+
+ r: process (sig)
+ begin -- process r
+ if sig'event then
+ report "Event on sig, new value = " & integer'image( sig );
+ end if;
+ end process r;
+
+end only;
diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
new file mode 100644
index 000000000..91e45ebc9
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/objects/signals/assignments/simple-integer-initialize.vhdl
@@ -0,0 +1,13 @@
+entity test_bench is
+end test_bench;
+
+architecture only of test_bench is
+ signal sig : integer := 0;
+begin -- only
+ p: process
+ begin -- process p
+ assert sig = 0 report "TEST FAILED" severity FAILURE;
+ report "TEST PASSED" severity NOTE;
+ wait;
+ end process p;
+end only;