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-rw-r--r--testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl24
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diff --git a/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl
new file mode 100644
index 000000000..97bc98508
--- /dev/null
+++ b/testsuite/vests/vhdl-93/clifton-labs/compliant/functional/std_logic_1164/test_std_logic_resolution_function.vhdl
@@ -0,0 +1,24 @@
+entity test is
+end test;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture only of test is
+ signal x, y, result : std_logic := '1';
+begin -- only
+ result <= x;
+ result <= y;
+
+ process
+ begin -- process
+ assert x = '1' report "TEST FAILED" severity failure;
+ assert y = '1' report "TEST FAILED" severity failure;
+ assert result = '1' report "TEST FAILED" severity failure;
+
+ report "TEST PASSED";
+-- x <= 'U';
+-- y <= 'U';
+ wait;
+ end process;
+end only;