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diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams new file mode 100644 index 000000000..f0ea59d1c --- /dev/null +++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/simultaneous_stmts/test183.ams @@ -0,0 +1,60 @@ + +-- Copyright (C) 2000-2002 The University of Cincinnati. +-- All rights reserved. + +-- This file is part of VESTs (Vhdl tESTs). + +-- UC MAKES NO REPRESENTATIONS OR WARRANTIES ABOUT THE SUITABILITY OF THE +-- SOFTWARE, EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE +-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, +-- OR NON-INFRINGEMENT. UC SHALL NOT BE LIABLE FOR ANY DAMAGES SUFFERED BY +-- LICENSEE AS A RESULT OF USING, RESULT OF USING, MODIFYING OR +-- DISTRIBUTING THIS SOFTWARE OR ITS DERIVATIVES. + +-- By using or copying this Software, Licensee agrees to abide by the +-- intellectual property laws, and all other applicable laws of the U.S., +-- and the terms of this license. + +-- You may modify, distribute, and use the software contained in this +-- package under the terms of the "GNU GENERAL PUBLIC LICENSE" version 2, +-- June 1991. A copy of this license agreement can be found in the file +-- "COPYING", distributed with this archive. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +-- --------------------------------------------------------------------- +-- +-- $Id: test183.ams,v 1.1 2002-03-27 22:11:20 paw Exp $ +-- $Revision: 1.1 $ +-- +-- --------------------------------------------------------------------- + +-- this model tests for the correst implementation of the 'above +-- statement. +PACKAGE electricalSystem IS + NATURE electrical IS real ACROSS real THROUGH; + FUNCTION SIN(X : real) RETURN real; + alias ground is electrical'reference; +END PACKAGE electricalSystem; + +use work.electricalsystem.all; + +entity product is +generic(bound:real:=1.0); +port( + quantity out1:real); +end product; + +architecture pro of product is +constant in1:real:=10.0; +constant in2:real:=1.0; +signal outofbound:out boolean; + +begin + outofbound<=true; + out1== in1*in2; + outofbound<=out1'above(bound); + +end pro; |