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Diffstat (limited to 'testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd')
-rw-r--r-- | testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd new file mode 100644 index 000000000..2b3b0f104 --- /dev/null +++ b/testsuite/vests/vhdl-ams/ashenden/compliant/digital-modeling/mux2.vhd @@ -0,0 +1,45 @@ + +-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc + +-- This file is part of VESTs (Vhdl tESTs). + +-- VESTs is free software; you can redistribute it and/or modify it +-- under the terms of the GNU General Public License as published by the +-- Free Software Foundation; either version 2 of the License, or (at +-- your option) any later version. + +-- VESTs is distributed in the hope that it will be useful, but WITHOUT +-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +-- for more details. + +-- You should have received a copy of the GNU General Public License +-- along with VESTs; if not, write to the Free Software Foundation, +-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + +entity mux2 is + port ( a, b, sel : in bit; + z : out bit ); +end entity mux2; + +-------------------------------------------------- + +architecture behavioral of mux2 is + + constant prop_delay : time := 2 ns; + +begin + + slick_mux : process is + begin + case sel is + when '0' => + z <= a after prop_delay; + wait on sel, a; + when '1' => + z <= b after prop_delay; + wait on sel, b; + end case; + end process slick_mux; + +end architecture behavioral; |